Serial to parallel Shift Registers

[Peter Nolan]

Hello,

I'm trying to understand serial to parallel registers in a effort to design
an RS232 generator.
If you look at figure 8 in this link:

http://www.trinary.cc/Tutorial/Registers/ShiftRegisters.htm

you will see a schematic of a serial to parallel register.
Suppose I put a fixed logic 1 on the data input and allow the let us say
three clock pulses to go through am I right in saying saying that I will end
up with a logic 1 at each output?

Peter Nolan.(humble novice in this group who occasionally gets his wires
crossed in his own speciality )
Dublin.

 

[Spehro Pefhany]

Hello,

I'm trying to understand serial to parallel registers in a effort to design
an RS232 generator.
If you look at figure 8 in this link:

http://www.trinary.cc/Tutorial/Registers/ShiftRegisters.htm

you will see a schematic of a serial to parallel register.
Suppose I put a fixed logic 1 on the data input and allow the let us say
three clock pulses to go through am I right in saying saying that I will end
up with a logic 1 at each output?

Yes. Suppose initial states are A, B, C:

Clocks Out0 Out1 Out2
0 A B C
1 1 A B
2 1 1 A
3 (or more) 1 1 1


Best regards,
Spehro Pefhany

 

[petrus bitbyter]

Hello,

I'm trying to understand serial to parallel registers in a effort to design
an RS232 generator.
If you look at figure 8 in this link:

http://www.trinary.cc/Tutorial/Registers/ShiftRegisters.htm

you will see a schematic of a serial to parallel register.
Suppose I put a fixed logic 1 on the data input and allow the let us say
three clock pulses to go through am I right in saying saying that I will end
up with a logic 1 at each output?

Peter Nolan.(humble novice in this group who occasionally gets his wires
crossed in his own speciality )
Dublin.

Peter,

Shortly: Yes. To understand take a step backward and learn the properties of
the positive edge-triggered D-flipflop.

petrus

 

[Naveed]

you will see a schematic of a serial to parallel register.

Suppose I put a fixed logic 1 on the data input and allow the let us say
three clock pulses to go through am I right in saying saying that I will end
up with a logic 1 at each output?

Yes.. That's the idea for serail to parallel.

 

[Peter Nolan]

Hello,


Thanks very much and you are right I need to study the positive
edge-triggered D-flipflop but will I actually end up understanding it I ask
myself?

Peter Nolan.
Dublin.

 

[Peter Nolan]

Hello,

I may barking up the wrong tree and need a parallel to serial converter and
not the other way around.
If you check out figure 9 of:

http://www.trinary.cc/Tutorial/Registers/ShiftRegisters.htm

I think that this is just what is required.
I found this link and many others that I didn't check:

http://www.philipslogic.com/products/shiftregisters/all/

Peter Nolan.
Dublin.