10 bit Parallel-in Serial-out Shift Register

Think about Steve's question.

 

What is the basic logic element that makes up a shift register?

How are they connected together to provide parallel input, serial input, shifting operation, parallel output, and serial output?

When you're creating a new device in a simulator or using an FPGA, it's helpful to look at existing devices (e.g. 74xx165, 74xx595) to see how they are implemented, but only so you can understand the internal parts of the device and how they work together to produce the specified behaviour for the device.

Once you understand that, you can design your shift register using the same arrangement, duplicated the number of times you want.

If you were designing a circuit to be built from existing devices, then you would need to worry about how to add blocks to the 165 or 595 (or whatever device you based your design around) to extend the number of bits. But in this case, it's simpler to break that device down into its component parts and reassemble a whole new "device" that does exactly what you want.

 

The bottom end of S1B is connected to earth! I don't know if that's why it isn't working, but it's wrong, so try fixing it!

Edit: Also, S3 is currently shorting VCC to earth as well.

 

You already have serial output; all you need is parallel input.

A simple way to add parallel input is to use the set and reset inputs of the flip-flops. You need to add a single parallel load signal, and a parallel data input for each flip-flop. Your logic needs to take these input signals and generate a set and reset signal for each flip-flop. When the parallel load signal is inactive, the set and reset signals to the flip-flops are held inactive. When the parallel load signal is active, each flip-flop is either set or reset depending on the state of its parallel data input.