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Serial to parallel Shift Registers

Discussion in 'Electronic Design' started by Peter Nolan, Feb 26, 2004.

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  1. Peter  Nolan

    Peter Nolan Guest


    I'm trying to understand serial to parallel registers in a effort to design
    an RS232 generator.
    If you look at figure 8 in this link:

    you will see a schematic of a serial to parallel register.
    Suppose I put a fixed logic 1 on the data input and allow the let us say
    three clock pulses to go through am I right in saying saying that I will end
    up with a logic 1 at each output?

    Peter Nolan.(humble novice in this group who occasionally gets his wires
    crossed in his own speciality :) )
  2. Yes. Suppose initial states are A, B, C:

    Clocks Out0 Out1 Out2
    0 A B C
    1 1 A B
    2 1 1 A
    3 (or more) 1 1 1

    Best regards,
    Spehro Pefhany
  3. Peter,

    Shortly: Yes. To understand take a step backward and learn the properties of
    the positive edge-triggered D-flipflop.

  4. Naveed

    Naveed Guest

    you will see a schematic of a serial to parallel register.

    Yes.. That's the idea for serail to parallel.
  5. Peter  Nolan

    Peter Nolan Guest


    Thanks very much and you are right I need to study the positive
    edge-triggered D-flipflop but will I actually end up understanding it I ask
    myself? :)

    Peter Nolan.
  6. Peter  Nolan

    Peter Nolan Guest

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