P
pdx
- Jan 1, 1970
- 0
How is the truth table for a JK flip flop derived from the circuit? I don't
understand it...
TIA.
understand it...
TIA.
pdx said:How is the truth table for a JK flip flop derived from the circuit? I don't
understand it...
TIA.
How is the truth table for a JK flip flop derived from the circuit? I don't
understand it...
TIA.
The classic TTL JKs would "catch ones"; if at any time the clock was
high and the J or K inputs went momentarily high in the "flip" sense,
it *would* flip on the next clock fall, even though the J/K had
returned low before the clock edge. Confused a lot of people.
John said:Does anybody still use JKs? I haven't used one in years, as a single
part or in an FPGA.
The classic TTL JKs would "catch ones"; if at any time the clock was
high and the J or K inputs went momentarily high in the "flip" sense,
it *would* flip on the next clock fall, even though the J/K had
returned low before the clock edge. Confused a lot of people.
John
This has nothing to do with the JK-FF. The original TTL family had many
parts with a strict master-slave architecture that specifically
prohibited certain input changes when the CLK was high. As for anyone
using them anymore, the JK was THE FF of choice for ASMs, whereas the D
FF was a natural for the much more versatile RTL architecture. The ASM
generally requires far more self-discipline than the average
semi-educated ape can muster, whereas the RTL is generalized enough to
absorb even the sloppiest quasi-thinking, hence the popularity of D's
and scarcity of JK's.
This has nothing to do with the JK-FF. The original TTL family had
many parts with a strict master-slave architecture that specifically
prohibited certain input changes when the CLK was high. As for anyone
using them anymore, the JK was THE FF of choice for ASMs, whereas the
D
FF was a natural for the much more versatile RTL architecture.
How is the truth table for a JK flip flop derived from the circuit? I don't
understand it...
TIA.
When I used to do hardware (not my area of interest), I seemFF was a natural for the much more versatile RTL architecture. The ASM
generally requires far more self-discipline than the average
semi-educated ape can muster, whereas the RTL is generalized enough to
absorb even the sloppiest quasi-thinking, hence the popularity of D's
and scarcity of JK's.
When I used to do hardware (not my area of interest), I seem
to remember that properly designed circuits with JK instead of D would
help to save a significant amount of logic. Most of the circuits that
I did were small (10-20 gates), and at that level, saving a few gates
with a JK was definitely helpful. For 'random' logic, I seldom saw
a real reason for NOT using a JK. The major reason for not using a
JK might be related to a lack of understanding or 'design concepts'
to fully utilize them.
Nowadays, the times that I'd use a CMOS/TTL (non FPGA/PAL/ROM or
microprocessor) logic based design would be very limited.
You always had to read the fine print with JKs. As I recall some JK that didFred Bloggs said:This has nothing to do with the JK-FF. The original TTL family had many
parts with a strict master-slave architecture that specifically
prohibited certain input changes when the CLK was high. As for anyone
using them anymore, the JK was THE FF of choice for ASMs, whereas the D
FF was a natural for the much more versatile RTL architecture. The ASM
generally requires far more self-discipline than the average
semi-educated ape can muster, whereas the RTL is generalized enough to
absorb even the sloppiest quasi-thinking, hence the popularity of D's
and scarcity of JK's.
I certainly admit that some of the JKs had 'personality', but there couldYou always had to read the fine print with JKs. As I recall some JK that did
ones catching on the J and K also had interaction between the clock and the
set/clear inputs.
John S. Dyson said:I certainly admit that some of the JKs had 'personality', but there could
be substantial gate savings when using a JK vs D 'random' logic design. If
using a microcode rom (or equivalent), then the benefit probable became nil.
So the death of the JK advantage probably appeared with the use of large
ROM type devices (or the mostly better yet programmable logic or PAL
stuff.) AFAIR, many old design techniques made some of the
hazard issues alot less troublesome than if doing ad-hoc designs. One
always has to carefully review the eccentricities, however.
It has probably been 20yrs since my last state machine design with
traditional (now probably ancient) random logic. The amount of flexibility
provided by microprocessors (and/or gate arrays of one kind or another)
would probably push the random logic designs (e.g. with ASM type techniqes)
into a very narrow niche. Way back when I did some sequencer designs
in hardware (before significant tools were commonplace), the similarities
between hardware and software were apparent.
The discipline of using well architected 'state machines' in software
or in hardware does translate to/from the simple logic designs of the
past (e.g. where one might use a JK) through a state machine that would
implement an internet server. An ad-hoc programming technique could
certainly cause quality problems in a product, and the hazards of
an ad-hoc hardware design can also cause 'problems.'
Again, I saw the 'advantage' of using JK flip flops as mostly a gate
count economy (where it might have been a little false because of the
complexity of the JK flip-flop interface.) D flip flops were certainly
more intuitive, but all but one or two designs that used JKs were
designed using well structured techniques.
(Using SSI 'gates' might have given a speed advantage in the early
1980's for simple designs, but it is incredible that in the 10-20nsec
for propagation in a saturated logic gate a Pentium4 can probably
do approx 10 floating point multiplications. A 74ls (or even 74AS) cannot
do much in the amount of time that a P4 can do a significant amount
of computation.)
John
I certainly admit that some of the JKs had 'personality', but there could
be substantial gate savings when using a JK vs D 'random' logic design. If
using a microcode rom (or equivalent), then the benefit probable became nil.
So the death of the JK advantage probably appeared with the use of large
ROM type devices (or the mostly better yet programmable logic or PAL
stuff.) AFAIR, many old design techniques made some of the
hazard issues alot less troublesome than if doing ad-hoc designs. One
always has to carefully review the eccentricities, however.
I didn't mean to do so -- but D flip-flops seem to be easier toThere's no reason to associate JKs with synchronous state machines and
Ds with ad-hoc async logic.