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High Precision Monostable

Discussion in 'Electronic Design' started by sergio108, Mar 11, 2008.

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  1. John Larkin

    John Larkin Guest


    A precision current source, charging an npo capacitor, feeding a fast
    comparator, can be stable to a few of 10's of PPM delay per degree C,
    with jitter of one part in 50,000 or better. That could just about do
    what he wants, if everything is done very carefully.
    LC delay lines tend to have bad tempcos, 100 ppm/degC or worse. And
    risetime:delaytime ratios are usually really bad, 1:10 sometimes, so
    expect a slow output edge, which may be hard to square up with
    precision. Not adjustable, either.

    The op hasn't mentioned rep-rate. If the trigger period is anywhere in
    the ballpark of the delay, and especially if the trigger rate changes,
    everything gets much worse... stuff can rattle around for a long time.

    John
     
  2. good idea John,

    http://www.google.com/patents?id=HlsfAAAAEBAJ&dq=4968907

    Patent number: 4968907
    Filing date: Nov 19, 1987
    Issue date: Nov 6, 1990

    Abstract
    An improved digital delay generator (10) for producing an output
    pulse/signal a preselected time interval after an input pulse/signal. The
    digital delay generator (10) of the present invention includes a single
    auxiliary timer (24) which starts responsive to feeding an input pulse
    thereto....

    thanks , Jure Z.
     
  3. sycochkn

    sycochkn Guest

    I guess it is 6000' feet of optical fiber then since it is 2008.

    Bob
     
  4. John Larkin

    John Larkin Guest

    The patent is a little obscure. The idea is to make a simple
    constant-current-capacitor-comparator ramp type delay, with a dac
    driving the other side of the comparator, to make a delay from, say, 0
    to 50 ns. That's simple. The trick is that one can then stop the
    current source for N clocks of a crystal oscillator, 50 MHz maybe,
    wait out any number of ticks, then resume and finish the timing. The N
    clocks of no-current extend the delay precisely (put a flat in the
    ramp) but add no jitter.

    The problems are mostly analog: charge injection, leakage, things like
    that. But it's simple and has a lot of nice properties.

    John
     
  5. John,
    I admit to not being aware of the Pepper patent until you
    mentioned it. What I suggested in my post was exactly an
    interrupted ramp generator.

    As you mnetion, the issues are related to : the integrator switching
    states ( integrate/hold/reset ), integrator errors such as droop or
    offsets in the hold mode, discriminator switching jitter, prop delays
    through logic and drivers, etc.

    To the extent that these errors are constant with time, temp,
    operating
    conditions, they imply a bias (offset) in the produced time
    interval.

    The potentially nasty situation is when the trigger signal comes
    synchronously with the local oscillator active edge, and the system
    may add ( or swallow) a whole clock period. That's why the
    synchronizers are needed.


    Thanks, Jure Z.

    PS : where is the OP , while we talk about "his" problem ?
     
  6. John Larkin

    John Larkin Guest

    Leakage into the "hold" cap is the big nasty. It's not a lot of pF,
    but you may want to freeze it for a long time. The SRS box has the
    same problem, essentially sample-and-hold leakage, which gets nasty
    for longer delays. In our design the clock-to-trigger information is
    stored digitally, so doesn't leak.

    The Pepper scheme adds flats within the ramp, never at the start, so
    clock-to-trigger alignment doesn't matter. Of course, you have to
    avoid metastability with a double-rank synchronizer or something, to
    decide when to insert the flats, but that's no big deal. If you make
    the ramp many (say, 5 or so) clocks long, there's no rush to let
    things settle and do the logic. Short delays are pure analog ramps, no
    clocked pauses at all. Very clever.




    <-------- net delay ----------->

    + < compare == done
    /
    /
    /
    /
    ____________________/
    / kill N clocks
    /
    /
    /
    /
    /
    ________________________/ < trigger



    Pepper was a better inventor than circuit designer. I have a
    reverse-engineered schamatic of his original box, and it's a
    nightmare. He floated most of the ECL logic 22 volts above ground, so
    it could directly switch current sources. Imagine debugging that!

    And the way he did output pulse widths was ghastly. A pot jams Vbe
    directly into a transistor, which becomes the current source for
    another ramp. Wide range log control on the pot!

    EG&G reportedly cleaned it up a few years back, but I don't know how
    extensive that was. EG&G was absorbed by Perkin-Elmer, who then spun
    off Signal Recovery, who still makes the box.
    OPs often disappear. But we can carry on!

    John
     
  7. whit3rd

    whit3rd Guest

    All true, but not convincing. The tempco depends on matching
    capacitor
    with ferrite, and can be bad OR very good. The risetime effect is a
    problem,
    but
    (a) 1:10 has been found, empirically, to often be 'good enough'
    (b) 1:30 or better is available (or used to be)
    (c) a true non-lumped-constant delay line is feasible which
    is devoid of that issue anyway.

    The rep-rate issue, though, is real. It takes some attention to
    driving
    and terminating impedances, and you'd still want to allow dead time
    between pulses. Ten delays should be enough; that would put a
    5 us pulse out, followed by a 'dead time' of 0.125 us, in the plan as
    outlined. Often, that's acceptable. It's likely to take as long
    to reset a timing capacitor.

    Gated delay-line oscillators are commercially available with 20 MHz
    output and circa .05%/C temperature drift. See

    <http://www.datadelay.com/datasheets/3d7701.pdf>
     
  8. John Larkin

    John Larkin Guest

    Yikes! Did they use their "novel and innovative" techniques to make
    the Vcc and temperature effects deliberately bad? It's not really
    difficult to do a gated LC oscillator that beats their stability specs
    by 10:1 or so. The LC will have less memory effects, too, totally
    forgetting any previous triggers in 1 to 2 cycles, rather than the
    "ten delays" this thing might need.

    A capacitor-based ramp could be reset in a fraction of the ramp time.


    John
     
  9. Fred Bloggs

    Fred Bloggs Guest

    Outrageous!
     
  10. whit3rd

    whit3rd Guest

    On Mar 12, 2:57 pm, John Larkin
    [ and a reference to a prepackaged delay line oscillator]
    Yeah, it's a pretty sloppy job all right. The commercial unit is just
    a gate
    for a driver, another gate for receiver, probably loosely impedance
    matched, and with gate-threshold thermal dependences builtin.
    A differential driver/receiver version would be much better.

    In the old days, one could stop an LC oscillator in a known phase with
    a peak-current source through the L and gated gain for the oscillator
    tube.
    It can still be done, but it requires a lot of quiescent current (with
    Q of
    100, a 1 mA LC oscillator has 100 mA of peak current in the L).
    Is that the 'gated oscillator' you're thinking of? Crystals, and LC
    oscillators, don't start abruptly unless one plays these tricks.

    Is there a good modern design (for my files) that you can cite?
     
  11. John Larkin

    John Larkin Guest


    HP did one delay generator that used a gated crystal oscillator, but
    it had a lot of problems. Crystals are hard to start and even harder
    to stop.

    The HP5359A Time Synthesizer used an ecl gated delay-line oscillator
    at roughly 100 MHz. I think the osc was a hybrid, with the delay line
    fabricated on the substrate. It took 75 ns to quench properly, 7.5
    times the oscillation period.


    An LC can be made to start instantly and stop very quickly.


    /
    /
    +----------o o-----R------+--------+----- out
    | | |
    | switch | |
    | | |
    - power L C
    + supply | |
    | | |
    | | |
    | | |
    gnd gnd gnd


    All you do is close the switch to quench the oscillations and charge
    up the inductor, then later open it to start. When the switch opens,
    you get a perfect sine that starts instantly from zero. The initial
    current and the Xl=Xc resonant impedance determine the oscillation
    amplitude. There is an optimum value of R to damp the oscillation
    quickly when you want to stop. I forget the exact value, but it's
    ballpark 0.7 times Xl. It's all very practical in the 50 MHz range
    with 10's of mA running through R when the switch is closed.

    Of course, you need a gain element somewhere to sustain the
    oscillations, and something to limit oscillation amplitude.

    We make four different digital delay generators that are based around
    gated oscillators like this. Three work in the 50 MHz range, and one
    at about 500. One of the units, not the 500, can work at trigger rates
    up to 20 MHz, which shows that you can start and stop one of these
    widgets fast. All have the LC tempco tweaked to below 20 PPM/degC; the
    500 MHz guy averages a few PPM.

    John
     
  12. JosephKK

    JosephKK Guest

    I disagree, a fast FPGA may do the job.
     
  13. JosephKK

    JosephKK Guest

    Something has gone funny here, my read of OP is generating them.
     
  14. John Larkin

    John Larkin Guest

    How would an FPGA generate a delay relative to an external trigger?

    Besides, fpga prop delays increase considerably with temperature, way,
    way more than the 0.01% required here.

    John
     
  15. MooseFET

    MooseFET Guest


    I don't think so. The delays in an FPGA drift quickly so the
    "staggered clocking" or "staggered edge" method won't hold to 100pS as
    the OP needs.
     
  16. JosephKK

    JosephKK Guest

    OP only needs 1/2 ns or 500 ps. Rather easier, but still not easy.
     
  17. JosephKK

    JosephKK Guest

    LC delay lines do not have to have bad tempco issues. I was measuring
    several makes of good ones about 25 years ago. Ovenizing them should
    be enough.
     
  18. MooseFET

    MooseFET Guest


    Still it is, I think a bit of a stretch for a FPGA. I'd expect a
    number somewhere around 1ns for FPGA nonclock delay matching.

    I have seen delays calibrated on the fly to about 1/3nS.
     
  19. JosephKK

    JosephKK Guest

    1 ns seems to be the current threshhold between doable and difficult.
    I remember when it was 10 ns.
     
  20. MooseFET

    MooseFET Guest

    Yes. These days 10nS is no longer as hard as it once was. At about
    100pS, you are certainly still into the RF components methods.
     
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