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High Precision Monostable

Discussion in 'Electronic Design' started by sergio108, Mar 11, 2008.

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  1. sergio108

    sergio108 Guest

    Hi All.
    We are working on a project where we need a very stable monostable to
    produce 5 microsecond pulses every time an input pulses arrive. We
    have tried IC 74123 and 74221 integrated circuits but the pulse width
    is not stable enough. Does anyone know a circuit or integrated circuit
    that produce high stable pulse width?. We need 5 microsecond pulses +-
    0.01%. Actually we work in a range from 1 to 10 microsecond pulse
    width.
    Thanks for your help or advice.
    Sergio
     
  2. Alan Peake

    Alan Peake Guest

    The 74HC series may be a little more stable but I'm not sure if they
    would be 0.01%
    I would use logic circuits - a shift register plus gates with a 100MHz
    clock. That won't get you 0.01% accuracy but it will give give you
    better than 0.01% stability which is what you appear to be asking for.
    Alan
     
  3. sycochkn

    sycochkn Guest

    Probably something with a crystal oscillator driving a counter that drives a
    latch on the output and the input trigger presets the counter and resets the
    latch.

    Bob
     
  4. sycochkn

    sycochkn Guest

    Or you could build it as a microcontrolller. Some prom a syncronous register
    and an oscillator.

    Bob
     
  5. MooseFET

    MooseFET Guest

    If the pulse must be timed to 0.01% WRT the edge of the input pulse:

    Delays based on LC circuits may be the way to go. RC circuits are
    never going to be accuarate enough. A crystal based circuit is ruled
    out by the 0.01% because you can't get 10GHz crystals. Basically you
    want a very accurate delay line.
     
  6. Guest

    ..01% = 1 / 10000 of 1uS = .1 nS (100 femto seconds) resolution.
    This would need a 10GHz clock, if you used a counter.

    You have a problem.
    I think even a good temp controlled oneshot in an oven will not do.
    Maybe one of the Giga Hz FPAG outputs......
    But I have not tried.
     
  7. Pico seconds :)

    resolution.
     
  8. Guest

    You need a precision comparator, a stable CR network and a noise free
    circuit. Noise and temp variations are the most likely causes of your
    problem. A digital approach is good if you dont need to make fine
    adjustments to the time period but its's not as simple as a clocked
    counter and a micro is out due to interrupt latency.
     
  9. John Larkin

    John Larkin Guest


    0.01% of 5 us is 100 PPM, namely 500 picoseconds. That's not the sort
    of stability you'll get from simple one-shot type circuits, or even a
    precision ramp/comparator. If you don't mind the initial output edge
    being synchronized to a clock, you could do this with a counter, with
    maybe a small additional analog delay to interpolate between clock
    ticks... but it will still be a challenge to hold 500 ps over
    temperature, and to keep the pulse-width jitter down.

    This will easily do it, but it's not cheap:

    http://www.highlandtechnology.com/DSS/T560DS.html

    What's the project?

    John
     
  10. Didi

    Didi Guest

    We are working on a project where we need a very stable monostable to
    If the 221 is not good enough, I would suspect you are using the wrong
    capacitors. I have used a 221 in a 13 bit Wilkinson-like ADC (a
    74HCT221
    was timing the integrate-up, about your range), and it worked fine.
    I was controlling the time with a DAC etc., and there were other
    sources
    of error, so I cannot claim to have measured it to be that precise but
    I would be very surprised if it is not - given my overall memories on
    that (designed > 10 years ago, http://tgi-sci.com/tgi/m321tb.htm ).

    Dimiter
     
  11. nospam

    nospam Guest

    When you can tell us how you intend to measure your pulses with 100pS
    resolution we can start believing your requirement.
    --
     
  12. Tim Wescott

    Tim Wescott Guest

    Square it up, run it through a delay line to an XOR gate? Delay lines
    have fallen out of style, so you may have to roll your own (although
    Digikey does have some that go up to 1us of delay -- at $8 a pop you'll
    only spend $80 to slap 10us of delay on the board, and then wonder if
    the part is good to 500ps).

    If this were 1960 I could just recommend 6000' of coax...

    I don't know if 74-anything is going to get you the precision you need
    -- I'd be studying data sheets and asking myself how many ways an
    otherwise working chip could be confused by noise and other effects.

    You're talking about 100ppm resolution here, at fairly high speeds.
    Don't be surprised if you have to flog things a bit to get the results
    you want.

    --

    Tim Wescott
    Wescott Design Services
    http://www.wescottdesign.com

    Do you need to implement control loops in software?
    "Applied Control Theory for Embedded Systems" gives you just what it says.
    See details at http://www.wescottdesign.com/actfes/actfes.html
     
  13. 100ppm with a opne shot is pushing it. However,
    there's a world of difference between the various
    manufacturer's designs, and some are definitely
    better than others, and some are much better.

    One suggestion, have you created a low-noise supply
    for your monostable? For a cmos part, this could
    just be an RC with a say 10 to 50ms time constant.

    Another suggestion, look at the Fairchild mm74hc123A,
    its datasheet shows very good stability. Another
    suggestion, the '4538 types of parts are claimed
    to be "precision" monostable timers.
     

  14. Sergio,

    a possible solution is to implement more or less a time to digital
    interpolator
    "backwards", (to deal with the async input).

    0) there is a stable enough (...?) clock running at, say 100 MHz ( T= 10
    ns)

    1) an async input trigger signal
    a) triggers a discriminator ( constant fraction ...?)
    b) starts an analog integrator
    c) sets the output

    2) the integrator is stopped and held at its value,
    on the next active edge of the 100 MHz clock

    3) a counter runs for an integer number of periods of the clock

    4) on the finalization of a prescribed count N,
    the integrator is restarted from where it was stopped in 2)

    5) the integrator runs until a comparator detects a voltage equivalent
    to T=10 ns

    6) the output is reset

    thre are a lot of fine details left for the dedicated reader to deal with...

    good luck !

    Jure Z.
     
  15. Guest

    As has been pointed out, 0.01% of 5usec is 500psec.

    Alan Peake suggested using a 100MHz clock; if you built your timing
    circuit with ON-Semiconductor's ECLinPS logic, you sould be able to
    get up to 700MHz. Vectron you can order a 700MHz crystal-controlled
    oscillator from Vectron

    http://www.vectron.com/products/xo/co437457.htm

    and there were other sources when I last looked (quite a few years
    ago).

    700MHz crystals aren't all that stable. If you want real stability,
    use a 700MHz voltage-pullable crystal-controlled oscillator such as
    this

    http://www.vectron.com/products/vcxo/c5310.pdf

    divide the ouptput down to 10MHz and use phase-locked loop to lock the
    700MHz to a high-stability 10MHz source.

    Getting 0.01% stability on the pulse width in such a system is a
    breeze.

    Obviously, the simple version of such a system can only start the 5
    microsecon pulse on the next clock edge after your trigger pulse,
    giving you a 1.43nsec jitter on the leading and trailing edges.

    I've built a system around an 800MHz clock, where we used a time to
    voltage converter to measure the off-set between the trigger and the
    clock, digitised it eight bits (5psec) and used a programmable delay
    to make the leading and trailing edges synchronous with the trigger to
    5nsec (in principle - in practice, the jitter through the system was
    about 100psec).

    It took some 40nsec before the digital data was available to correct
    the leading edge of the pulse.

    The scheme we used to generate the programmable delay involved
    discharging a capacitor and setting up a threshold with a D/A
    converter; today you might use an ECLinPS digitally programmable delay

    http://www.onsemi.com/pub_link/Collateral/MC10E195-D.PDF

    http://www.onsemi.com/pub_link/Collateral/MC10EP195-D.PDF

    The actual delays generated are temperature dependent; you'd probably
    have to build in automatic self-calibration (we did) but you might be
    able to getting away with putting it into a crystal oven, or
    stabilising the temperature closer to room temperature by putting a
    Peltier junction on the top of the package.
     
  16. John Larkin

    John Larkin Guest

    That's similar to the way the SRS DG535 delay generator works. The
    trigger is run into a clocked dual-rank syncronizer, basically a 2-bit
    shift register. It produces a pulse that's between 1 and 2 clocks
    wide, which drives a holdable analog ramp. Then they tick off N clocks
    and go into another analog ramp as the fine delay. The voltage from
    the input ramp is added to the target voltage of the output ramp,
    theoretically cancelling the input trigger-to-clock jitter. It
    involves a lot of analog storage, but works fairly well for short
    delays. Any errors in matching the ramp slopes become jitter. They run
    at 80 MHz, I seem to recall.

    The Signal Recovery delay generator uses the fiendishly clever
    Pepper-patent interrupted ramp technique, much simpler.

    John
     
  17. John Larkin

    John Larkin Guest

    HP5370B, from ebay: 25 ps single-shot resolution, much better with
    averaging.

    Lots of counters can get down to 100 ps with averaging. A decent
    sampling scope, like an 11801, can do this too. 100 ps is a barn door
    in this business.

    Besides, maybe he doesn't have to measure them exactly. Maybe he just
    needs them to be stable.

    John
     
  18. John Larkin

    John Larkin Guest

    Both passive and silicon delay lines have awful temperature
    coefficients, and both will have lots of jitter in the real world.
    Bad TC again, and maybe jitter, since the output risetime will be
    terrible.

    Fiber optics would be better, no jitter to speak of, tiny size and
    weight, but not adjustable. Figure roughly 15 ppm per degree C
    delay/temp coefficient.

    John
     
  19. Rich Grise

    Rich Grise Guest

    He didn't say anything about resolutionn - he wants +-0.01 percent
    _stability_, which to my mind doesn't rule out a clock, if it's
    stable enough.

    Really, I don't think he's got a knob calibrated 5, 5.01, 5.02, etc.

    Hope This Helps!
    Rich
     
  20. whit3rd

    whit3rd Guest

    The use of a single monostable means you have low slew rate and
    the slightest (thermal) noise can shift the trigger time. The gurus
    on
    high precision timing tell me "we don't use monostables".

    LC timing is somewhat better, and LC delay lines are a good choice
    here.
    You want to make a triggered oscillator and synchronous counter,
    like a NAND with output through a delay line to input 1; it oscillates
    starting at known phase when input 2 is taken high. Pick a high-ish
    frequency (20 MHz) and it needs only a 25 ns delay line. Use a few
    meters of coax cable if you can't find a packaged delay line.

    A divide-by-N 20 MHz counter is just a couple of 74ALS161's, and a
    flip/flop that is SET at the start time, then RESET on the target
    count. The Q from that flip/flop, of course, drives the NAND input 2
    line... and the \Q loads the N value...
     
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