It's not normally a good idea to do anything time-consuming in an ISR. Also, any I/O accesses and variable accesses made by an ISR need to be carefully considered. What happens if the IRQ happens while your mainline code is in the middle of an SPI communication to that IC? Or a different SPI device that you might add in future? If the interrupt handler accesses the SPI signals, it will fail to communicate with the SPI device, and it will disrupt the mainline's communication as well.
A better way is to use bitflags ("semaphores") to allow your interrupt handler to signal to the mainline that there is work to be done. The mainline can run around in an "event loop", checking each semaphore in turn and calling a function to deal with the event if the semaphore is set.
In this case, you don't even need an interrupt handler, because the PIC hardware will keep the interrupt request flag (in PIR1 or wherever it is) set until cleared by software. So that's the semaphore you need, right there.
You should find out what the nRF does with the interrupt signal. Does it require data to be read from it before it releases the IRQ line back high again? Or does it just pulse it low briefly? If the former, you will have to perform the required SPI action before you can safely reset the interrupt request flag.
Another technique that's useful in real-time applications with multiple simultaneous inputs and outputs is queues, or circular buffers. This is an area of memory that's used as a FIFO (first in, first out) buffer for communication between two independent tasks. The data in the queue may be fully formed messages, status codes, command bytes, or whatever is appropriate. The queue is managed with two pointers: a "put" pointer and a "get" pointer, which point to where data will be added and removed, respectively. When either pointer passes the top of the memory area reserved for the queue, it is reset to the bottom of that area. When the pointers are equal there is no data in the queue. Google for more information.