What is the jelly bean DAC du jour?

[Fred Bartoli]

Joerg a écrit :

Hello Spehro,


Currently I am looking at the MSP430. There is only one timer on most of
these, with 2-3 CCRs. If it doesn't have to do anything else I could add
more in assembler. The need to listen to some kind of bus for value
changes throws that a curve though. Plus in this case I'd have to filter
them LC because the wee corners of an RC need to be muffled. Has to be
whisper quiet.

So why going PWM?
Just use one output port and 8 sigma-delta sequenced on a fast interrupt.

BTW the Mega AVRs have 4 timers: 2x8 bits with 1 OCR each, and 2x16 bits
with 3 OCR each, giving you the wanted 8 PWM output if you don't like
the better SD

 

[Joerg]

Hello Fred,

So why going PWM?
Just use one output port and 8 sigma-delta sequenced on a fast interrupt.

Yes, that would muffle the noise much better. Too much use of interrupts
is frowned upon by embedded guys though and I will ultimately have to
hand the firmware off to one of them.

BTW the Mega AVRs have 4 timers: 2x8 bits with 1 OCR each, and 2x16 bits
with 3 OCR each, giving you the wanted 8 PWM output if you don't like
the better SD

That's nice, especially since the WDT on the MSP can't really be used
for PWM too well. It isn't very flexible.

 

[linnix]

So why going PWM?
Just use one output port and 8 sigma-delta sequenced on a fast interrupt.

The old fashion way (op amp integrator) is far lower in noise and power
consumption. You can easily build 4 channels per
PIC/AVR/MSP/LPC/ARM/CPLD.

 

[Arlet]

So why going PWM?
Just use one output port and 8 sigma-delta sequenced on a fast interrupt.

BTW the Mega AVRs have 4 timers: 2x8 bits with 1 OCR each, and 2x16 bits
with 3 OCR each, giving you the wanted 8 PWM output if you don't like
the better SD

On an AVR, If you forget about the interrupt, just poll in a loop, and
dedicate a bunch of registers to the sigma-delta algoritm, I think you
can do 8 outputs in about 40 cycles. That doesn't leave any time yet to
check a serial port for new commands.

Joerg said he wanted low-noise, though. Not sure if this qualifies.

 

[Joerg]

Hello Linnix,

But the basic functions never change. I can implement the same shift
registers using PLA equations as well as VHDL. In fact, I almost
always use the same serial (micro side) / parallel (i/o side) shift
registers for CPLD. CPLD would get cheaper with higher volume. Below
$1 for the XC9572XL might be possible. I would rather overstock on
CPLD then custom DACs.

As long as there isn't that post-it note from Purchasing on your desk
some day, stating that they can't get any on the market right now.

If you really need the low power (more expensive), cool runner II need
12uA @1.8V for standy You can run at very low frequency and the only
power would be driving the op-amp integrators. I don't think custom
DACs would be any better.

uCs are a lot lower but that level would certainly be acceptable in this
case. As long as they don't require too much babying with the power
rails. At one clients this week I saw one that needed three (!)
different voltages and they had to come on in a very prescribed order.
So they had to use a special regulator chip. But this was a really big
programmable.

 

[Fred Bartoli]

Joerg a écrit :

Hello Fred,


Yes, that would muffle the noise much better. Too much use of interrupts
is frowned upon by embedded guys though and I will ultimately have to
hand the firmware off to one of them.

I thought more of having one dedicated small uC, like some TinyAVRs.
The Tiny2313 in a 20 pin package will give you 16IOs, minus 2 or 3 for
the serial command bus. That's 14/13 left. Not too bad.

 

[Joerg]

Hello Arlet,

On an AVR, If you forget about the interrupt, just poll in a loop, and
dedicate a bunch of registers to the sigma-delta algoritm, I think you
can do 8 outputs in about 40 cycles. That doesn't leave any time yet to
check a serial port for new commands.

Joerg said he wanted low-noise, though. Not sure if this qualifies.

It would qualify since filtering the outputs would become pretty easy.
EMI from the uC itself is something I am used to deal with.

 

[Joerg]

Hello Fred,

I thought more of having one dedicated small uC, like some TinyAVRs.
The Tiny2313 in a 20 pin package will give you 16IOs, minus 2 or 3 for
the serial command bus. That's 14/13 left. Not too bad.

That would be an option. But then I might as well place a an octal DAC
next to the main uC. It doesn't need any firmware written for it ;-)

 

[Arlet]

It would qualify since filtering the outputs would become pretty easy.
EMI from the uC itself is something I am used to deal with.

This is a piece of code I had in mind. Use r0-r7 for the accumulators,
and r8-r15 for the PWM values. Then make a loop like this:

loop:
clr r16
add r0, r8
brcc l0
ori r16, #0x01
l0:
add r1, r9
brcc l1
ori r16, #0x02
l1:
// repeat for r2/r10, r3/r10.. until r7/r15

out PORTx, r16

// check UART/SPI slave, if any data, write to r8..r15, using the
fact that these are memory mapped.
rjmp loop

Each output takes 3 instructions/4 cycles, plus some loop overhead.
Output ranges from 0..255, so you can't reach the rail.

You can also put this in a timer interrupt, so it's easier to do other
stuff, but then you'll have additional overhead.

 

[linnix]

Hello Linnix,


As long as there isn't that post-it note from Purchasing on your desk
some day, stating that they can't get any on the market right now.


uCs are a lot lower but that level would certainly be acceptable in this
case. As long as they don't require too much babying with the power
rails. At one clients this week I saw one that needed three (!)
different voltages and they had to come on in a very prescribed order.
So they had to use a special regulator chip. But this was a really big
programmable.

Again, you are thinking FPGA. Cool runner CPLDs are single supply
(1.8V), flash based. No external chips required. They are just the
lower VCC version of XC9500. We are just about getting a batch of
XC9536XL (44 pins) for a bit more than $1 each. If you switch the
op-amp feedback, you might be able to get away with single macrocell
registers. In that case, you can build three to four channels for each
chip.

We usually build double macro-cell registers, so I suggested XC9572XL
earlier.

 

[Arlet]

Again, you are thinking FPGA. Cool runner CPLDs are single supply
(1.8V), flash based. No external chips required. They are just the
lower VCC version of XC9500. We are just about getting a batch of
XC9536XL (44 pins) for a bit more than $1 each. If you switch the
op-amp feedback, you might be able to get away with single macrocell
registers. In that case, you can build three to four channels for each
chip.

We usually build double macro-cell registers, so I suggested XC9572XL
earlier.

FPGAs can still be interesting if you need a *lot* of outputs. A small
spartan-3 could do >100 outputs for $20. Assuming top speed is not
required, you can implement the sigma-delta around a block RAM, and do
a bunch of outputs sequentially, saving a ton of flipflops. Dynamic
power requirements would be low, since not much is happening inside.

 

[John B]

On 08/11/2006 the venerable Joerg etched in runes:

Hi Joerg,

Hello Folks,

Haven't used DACs in a while, did it with PWM all the time. Now I
need to design something that requires lots of low noise DC levels to
be set.

What is the common jelly-bean 8-bit multi-DAC with a serial bus these
days?

The requirements would be the usual. Multi-sourced if possible, lots
of channels, under 50c/channel or at least under $1/channel, 8 bits
or more, serial bus with two or at the most three wires, speed can be
in the low kHz range. A chip select would be nice but that could also
be handled by gating logic.

I have seen some nice octal 8-bitters like the TLC5628 which
unfortunately needs an extra load command line (but that would be
ok). Don't know whether that one is a mainstream part and I want to
avoid settling for a boutique part, which is why I am asking.

Then there'll be the challenge to bus the data to several dozen
modules with the DACs on them but that's a whole 'nother matter. Got
to wait until the guys tell me what the bus is going to be. Hopefully
nothing that needs lots of arbitration.

You don't say what supply you're using but I've had a lot of success
with MAX533 (2.7V) & MAX534 (5V). Both quad 8-bit SPI at <$3.

 

[linnix]

FPGAs can still be interesting if you need a *lot* of outputs. A small
spartan-3 could do >100 outputs for $20. Assuming top speed is not
required, you can implement the sigma-delta around a block RAM, and do
a bunch of outputs sequentially, saving a ton of flipflops. Dynamic
power requirements would be low, since not much is happening inside.

Not so, I believe that you need to constantly maintain the Sigma-Delta
(or Delta-Sigma) signals.

There are really two separate issues here:

1. FPGA vs. MICRO/CPLD

I argue that MICRO/CPLD would be cheaper and simpler to implement.

2. Delta Sigma vs. Parallel Junction (or give me another term).

I argue that Parallel Junction would have less noise problems and less
dependences on external analog components. Delta Sigma would requires
external filters and these components to determine the output signals,
integrated over time. Parallel Junction is a linear adder.

 

[Arlet]

Not so, I believe that you need to constantly maintain the Sigma-Delta
(or Delta-Sigma) signals.

The sequential approach is also maintained constantly, just at a lower
frequency. If you do 10 outputs in round-robin fashion, they'll be
updated at 1/10 the frequency, say 10MHz instead of 100MHz. The output
bit pattern itself is identical, just slower. If you don't require high
frequency analog signals, and don't mind the bigger filter, it'll work
fine.

There are really two separate issues here:

1. FPGA vs. MICRO/CPLD

I argue that MICRO/CPLD would be cheaper and simpler to implement.

2. Delta Sigma vs. Parallel Junction (or give me another term).

I argue that Parallel Junction would have less noise problems and less
dependences on external analog components. Delta Sigma would requires
external filters and these components to determine the output signals,
integrated over time. Parallel Junction is a linear adder.

Sounds interesting. Can you explain how this 'parallel junction' dac
works ?

 

[Joerg]

Hello John,

You don't say what supply you're using but I've had a lot of success
with MAX533 (2.7V) & MAX534 (5V). Both quad 8-bit SPI at <$3.

Thanks, but I'd like to avoid this brand. Had way too many instances
where clients called me to design Maxim chips out of existing products
because they simply could not secure large quantities in a timely manner.

VCC is wide open. At this point I can provide anything that is needed.
The good thing about this project is that I can pick a blank sheet and
start. The usual requests are making something work that already exists
and with the least amount of changes, but luckily that's not the case here.

 

[Joerg]

Hello Arlet,

This is a piece of code I had in mind. Use r0-r7 for the accumulators,
and r8-r15 for the PWM values. Then make a loop like this:

loop:
clr r16
add r0, r8
brcc l0
ori r16, #0x01
l0:
add r1, r9
brcc l1
ori r16, #0x02
l1:
// repeat for r2/r10, r3/r10.. until r7/r15

out PORTx, r16

// check UART/SPI slave, if any data, write to r8..r15, using the
fact that these are memory mapped.
rjmp loop

Each output takes 3 instructions/4 cycles, plus some loop overhead.
Output ranges from 0..255, so you can't reach the rail.

You can also put this in a timer interrupt, so it's easier to do other
stuff, but then you'll have additional overhead.

SW-PWM is certainly one option I am going to look at. It would
definitely have to run in a timer interrupt even if I'd dedicate one uC
to do nothing but PWM. The reason is that some of those PWM will be in a
PID loop and within phase-lockers. The remaining code would be quite
lean so that I could comfortably saddle the uC with PWM to up to 50% of
its horsepower. If the PID runs in another uC all that remains is port
reads and then I could go even higher.

 

[Arlet]

SW-PWM is certainly one option I am going to look at. It would
definitely have to run in a timer interrupt even if I'd dedicate one uC
to do nothing but PWM. The reason is that some of those PWM will be in a
PID loop and within phase-lockers. The remaining code would be quite
lean so that I could comfortably saddle the uC with PWM to up to 50% of
its horsepower. If the PID runs in another uC all that remains is port
reads and then I could go even higher.

Ok. If you other code is lean enough, and you write it in asm, you can
even put my routine in an interrupt handler, and globally reserve
r0-r16 for it. The rest of the code must then be written to only use
r17-r31.

 

[linnix]

I don't know what the term is exactly, but it's how we implement D2As
other than Delta Sigma.

You can take a XC9536 (36 macrocells) and make 4 8 bits up/down
counters (plus some other logics). As long as your target values does
not change much, there is only incremental countings. So most of the
time, the chip is idle.

You can wire the outputs via R-networks and op-amp summing junctions.
So, you need 1/4 XC9536, 8 resistors and one op-amp per channel. It
could be less than 50 cents each.

 

[Joerg]

Hello Arlet,

Ok. If you other code is lean enough, and you write it in asm, you can
even put my routine in an interrupt handler, and globally reserve
r0-r16 for it. The rest of the code must then be written to only use
r17-r31.

I am not a code expert, more a HW guy. But I guess that would require
going to Atmel. AFAICT the regular size MSP430 versions do not have that
many registers. But I guess one could use RAM writes here and accept a
coarser PWM as long as the number of clock cycles is always the same.

 

[Tony]

Will a fast delta-sigma modulator on a CPLD or small FPGA be able to
match your requirements ? You can fairly easily roll your own, and get
plenty of channels out of a single part.

I've been searching for a while for some tips to roll at least 12
channels of SD ADCs into an FPGA, with external 2nd order modulators
(mostly because the audio ADCs' PGAs aren't guaranteed stable enough
for me over -400C to +60C, and the simple sinc3 decimation filters in
industrial ADCs don't have the alias rejection I need). Any tips or
links appreciated, on the FPGA approach or on better ADCs.
Tony (remove the "_" to reply by email)