Variable amplitude clock?

[jdhar]

Sometimes Hi-Z, but other times it may have to drive a clock receiver
that is actually expects a current drive. Overdriving it with a little
higher voltage is fine for the case where a current is expected... but
with a current drive receiver, the passive solution won't work.

 

[jdhar]

I'm still trying to debate whether a fast slew-rate VGA or one of
those buffers is the way to go.

Some of the VGAs have slew rates of 13V/ns, which I think would be
fast enough for my application. The advantage is that they can also
produce a differential signal which is key. What worries me is I do'nt
know what the clock will look like since I have never put a square
wave through an opamp before :S

The digital logic solutions would reproduce the clock quite nicely at
the levels I want, but I'm afraid that there would be mismatch if I
use 2 to buffer a diff. signal. Is this a valid concern?

 

[Joerg]

I'm still trying to debate whether a fast slew-rate VGA or one of
those buffers is the way to go.

Some of the VGAs have slew rates of 13V/ns, which I think would be
fast enough for my application. The advantage is that they can also
produce a differential signal which is key. What worries me is I do'nt
know what the clock will look like since I have never put a square
wave through an opamp before :S

It pretty much comes out at the slew rate.

The digital logic solutions would reproduce the clock quite nicely at
the levels I want, but I'm afraid that there would be mismatch if I
use 2 to buffer a diff. signal. Is this a valid concern?

Using an extra inverter in one line causes a propagation delay for that
line and not the other but with modern logic such as AUC or AUP that
won't be much, a few nsec maybe. Also, if that's a concern you can
LC-delay the other.

 

[John Larkin]

Thanks John. I think that wouldn't work in the case where the clock
receiver pulls any current since it's just a passive divider, correct?
Taht would only work in the High-Z case.

The most the impedance will be is around 50 ohms, with the pot at
mid-scale, so this will drive nearly any logic family.

John

 

[Fred Bloggs]

Thanks. They don't have the AUP family by they mention the AUC famil;y
to be overvoltage tolerant up to 3.3V.

The AUP can take 3.6V inputs at any Vdd...that is in the AUP family summary.

 

[Fred Bloggs]

I'm still trying to debate whether a fast slew-rate VGA or one of
those buffers is the way to go.

Some of the VGAs have slew rates of 13V/ns, which I think would be
fast enough for my application. The advantage is that they can also
produce a differential signal which is key. What worries me is I do'nt
know what the clock will look like since I have never put a square
wave through an opamp before :S

The digital logic solutions would reproduce the clock quite nicely at
the levels I want, but I'm afraid that there would be mismatch if I
use 2 to buffer a diff. signal. Is this a valid concern?

You're keeping us guessing here, there are any number of possible
solutions, but we'll never know what is reasonable from your limited
description. The simplest logic gate solution would be as shown below,
try to avoid anything that mentions Schmitt trigger inputs, these spell
disaster for low jitter, they're real bad actually...
View in a fixed-width font such as Courier.

 

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This would only work with a matched load, right?

Yup.