Painless micro program

[MooseFET]

[email protected] says... [... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of a
screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.

A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.

MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.


[... about keyboards ...]

Which is why I put 8048 in quotes. My bet is that the 8048 core is
still in there.

I wonder if they've gone so far as to look at the code to see which
instructions actually got used an only implemented that much of the
8048.

 

[John Larkin]

[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of a
screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.

A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.

MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.

Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

and the MSP430 is essentially the same, executing the sequence in
about 400 ns. Both machines allow a choice of relative (relocatable)
or absolute addressing. The rumor is that a few guys invented the
PDP-11 architecture one night in Gordon Bell's basement.

On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John

 

[John Larkin]

There's nothing wrong with ladder logic. Although I've not programmed
exensively in it, I've designed products that accept forms of it.
People who are drawn to graphic representations rather than procedural
languages might even prefer it, despite the electromechanical
paradigm. Having a 'hardened' hardware platform is certainly worth
something in many situations too.

Several of my customers program my (sometimes hairy) VME modules in
ladder logic, and seem to do at least as well as "real" programmers.
Their "code" seems to be fairly portable, too. And I think, from what
I know, ladder logic is uncrashable.

John

 

[MooseFET]

[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of a
screamer either (12 clocks per op, as well).
There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:
Like I said, there isn't much of a difference.
A = B + C
Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.
The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.

MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.

Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

For the PDP-8 it was:

CLA ; Clearing then adding is the
TAD I PointerToB ; .. way you load values
TAD I PointerToC ; The I makes it indirect address
DCA I PointerToA ; Store the result.

For a machine with, most likely, less hardware than an 1802, this is
quite good. The folk at DEC spent a huge amount of time working out
the best posible use of the number of transistors allowed.

For the 8086:

MOV DS,SEGMENT B ; 1
MOV AL,[DS:OFFSET B] ; 2
MOV DS,SEGMENT C ; 3
ADD AL,[DS:OFFSET C] ; 4
MOV DS,SEGMENT A ; 5
MOV [DS:OFFSET A],AL ; 6



[....]

There weren't many triple-operand machines around, ever.

You have to get into the Very Long Instruction Word machines before 3
operands makes much sense. There is little point in making an
instruction that takes 4 memory cycles to load that does the same as
two shorter instructions.

 

[John Larkin]

[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of a
screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.

A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.

MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.

Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

For the PDP-8 it was:

CLA ; Clearing then adding is the
TAD I PointerToB ; .. way you load values
TAD I PointerToC ; The I makes it indirect address
DCA I PointerToA ; Store the result.

Or just

CLA
TAD B
TAD C
DCA A

if the operands were on page 0 or on the current page.

For a machine with, most likely, less hardware than an 1802, this is
quite good. The folk at DEC spent a huge amount of time working out
the best posible use of the number of transistors allowed.

Yeah, but no indexing and no stack! Reentrancy gets dicey.

JSR poked the return address into the first word of the subroutine! A
sub returned by jumping indirect through its own entry point!

The PICs seem to be 8 ripoffs, sort of.

John

 

[MooseFET]

On May 20, 2:30 pm, John Larkin

Or just

CLA
TAD B
TAD C
DCA A

I wasn't allowing any special cases because there are special cases
for each that have different restrictions. If the three values are in
a row in memory, the 1802 doesn't look nearly as bad.

Yeah, but no indexing and no stack! Reentrancy gets dicey.

You are free to make your own stack using the "auto increment"
locations. The interrupts only need to be off for a little while.

BTW: You do have indexing or sorts. Any direct memory location can
index you to any location in the current field.

 

[joseph2k]

[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of
a screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.



A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.

MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.

Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

and the MSP430 is essentially the same, executing the sequence in
about 400 ns. Both machines allow a choice of relative (relocatable)
or absolute addressing. The rumor is that a few guys invented the
PDP-11 architecture one night in Gordon Bell's basement.

On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John

I actually have worked with a machine that used up to 7 operands for a
single instruction. IIRC the instruction was a repeated move selective
replace using different source and destination indexes, different base
address (with a special interpretation for one), a mask value, replace
value, and iteration count.

 

[John Larkin]

[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of
a screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.



A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.


MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.

Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

and the MSP430 is essentially the same, executing the sequence in
about 400 ns. Both machines allow a choice of relative (relocatable)
or absolute addressing. The rumor is that a few guys invented the
PDP-11 architecture one night in Gordon Bell's basement.

On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John

I actually have worked with a machine that used up to 7 operands for a
single instruction. IIRC the instruction was a repeated move selective
replace using different source and destination indexes, different base
address (with a special interpretation for one), a mask value, replace
value, and iteration count.

Yikes!

Some of the CISC-ier machines, like HP 3000 and Vax and the nearly
forgotten, failed 32-bit Intel chip (what was that called?) had
outrageous instructions, like polynomial eval and hairy string ops,
but that was just tons of microcode so doesn't really count, by my
official decree. The 68332 even has a few, like the linear
interpolation thing and hi/lo limit checks.

John

 

[Robert]

John Larkin wrote: [snip]

On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John

I actually have worked with a machine that used up to 7 operands for a
single instruction. IIRC the instruction was a repeated move selective
replace using different source and destination indexes, different base
address (with a special interpretation for one), a mask value, replace
value, and iteration count.

Yikes!

Some of the CISC-ier machines, like HP 3000 and Vax and the nearly
forgotten, failed 32-bit Intel chip (what was that called?) had
outrageous instructions, like polynomial eval and hairy string ops,
but that was just tons of microcode so doesn't really count, by my
official decree. The 68332 even has a few, like the linear
interpolation thing and hi/lo limit checks.

John

The 432 or its successor the i960?

http://www.microprocessor.sscc.ru/great/s6.html

Robert

 

[John Larkin]

John Larkin wrote: [snip]
On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John
I actually have worked with a machine that used up to 7 operands for a
single instruction. IIRC the instruction was a repeated move selective
replace using different source and destination indexes, different base
address (with a special interpretation for one), a mask value, replace
value, and iteration count.

Yikes!

Some of the CISC-ier machines, like HP 3000 and Vax and the nearly
forgotten, failed 32-bit Intel chip (what was that called?) had
outrageous instructions, like polynomial eval and hairy string ops,
but that was just tons of microcode so doesn't really count, by my
official decree. The 68332 even has a few, like the linear
interpolation thing and hi/lo limit checks.

John

The 432 or its successor the i960?

http://www.microprocessor.sscc.ru/great/s6.html

Robert

I was thinking of the 432, too elegant and too slow. The HP3000 was a
similar stack-operating machine with a lot of high-level constructs,
and started out almost fatally slow, although they eventually got it
up to speed and sold a lot into banking and such.

I wonder if Itanic will survive?

Strange that we wound up with the kluge that is x86.

John

 

[MooseFET]

On May 20, 9:06 pm, John Larkin

[....]

I was thinking of the 432, too elegant and too slow. The HP3000 was a

The 432 was a classic case of a plan based on a fatal flaw. The 432
required two memory operations for a memory access. It had to look up
in the table what the value could be used for etc and then get the
actual value. This slowed it down a lot.

It was an attempt to make a processor that was "safe". In theory,
your program couldn't go too far astray before the hardware caught an
illegal operation.

They missed the performance mark and kept many bright people at Intel
too busy to work on a processor that would meet what the market needed
in the short term.

[....]

Strange that we wound up with the kluge that is x86.

It was, I think, those who weren't good enough to be let onto the 432
team that designed the 8086. It would have been better if they had
just taken the 8080 design and doubled most of the registers etc.

 

[Rich Grise]

[email protected] says... [... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much of a
screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

A = B + C

Compiles to something like 16 instructions if A, B and C are randomly
located in the RAM area.

[....]

Not very. Almost every computer keyboard on the planet has an
"8048" in it.

I think today it is more of a 8048 like core in a special chip. I
wouldn't be surprised to see only one package inside a keyboard. With
the kind of quantity they are made in today a special purpose IC makes
a lot of sense.

I've seen at least three different brands that look very much like this:
http://www.neodruid.net/KeyZilla/Keyboard3.html

Cheers!
Rich

 

[Rich Grise]

There weren't many triple-operand machines around, ever.

In microprogrammable machines, three operands are almost routine,
sometimes four: src A, src B, dest, and next instruction address.

They're fun!

Cheers!
Rich

 

[John Larkin]

Ick! Having a stack (not all processors have one) and not being able
to push some resources to it is really ugly! How do they suggest
that this be handled? What was the rationale/excuse for not being
able to push an index?

Dunno. They fixed it on the 6803.

In its defense, on an external interrupt or an SWI trap, the 6800/6802
pushed all the registers (including the index) and the pc and the ps,
all automatically, which is sort of a hardware context save. That made
the RTOS situation sort of neat: on entry to the scheduler, from a
hard or soft interrupt, all you had to do was save the task stack
pointer in the job header, and then you could reschedule and run the
hottest task, or just RTI back into the previous one.

John

 

[joseph2k]

[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much
of a screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.



A = B + C

Compiles to something like 16 instructions if A, B and C are
randomly located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.


MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.


Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

and the MSP430 is essentially the same, executing the sequence in
about 400 ns. Both machines allow a choice of relative (relocatable)
or absolute addressing. The rumor is that a few guys invented the
PDP-11 architecture one night in Gordon Bell's basement.

On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John

I actually have worked with a machine that used up to 7 operands for a
single instruction. IIRC the instruction was a repeated move selective
replace using different source and destination indexes, different base
address (with a special interpretation for one), a mask value, replace
value, and iteration count.

Yikes!

Some of the CISC-ier machines, like HP 3000 and Vax and the nearly
forgotten, failed 32-bit Intel chip (what was that called?) had
outrageous instructions, like polynomial eval and hairy string ops,
but that was just tons of microcode so doesn't really count, by my
official decree. The 68332 even has a few, like the linear
interpolation thing and hi/lo limit checks.

John

I think the old intel processor you are talking about the i432 "MicroFlame".
IIRC it was a four or five chip group for the processor (kinda like a 2901
bit slice machine) and about a 11 by 14 board full of TTL logic (kinda like
the old IBM PC or XT).

 

[joseph2k]

On May 20, 9:06 pm, John Larkin

[....]

I was thinking of the 432, too elegant and too slow. The HP3000 was a

The 432 was a classic case of a plan based on a fatal flaw. The 432
required two memory operations for a memory access. It had to look up
in the table what the value could be used for etc and then get the
actual value. This slowed it down a lot.

It was an attempt to make a processor that was "safe". In theory,
your program couldn't go too far astray before the hardware caught an
illegal operation.

They missed the performance mark and kept many bright people at Intel
too busy to work on a processor that would meet what the market needed
in the short term.

[....]

Strange that we wound up with the kluge that is x86.

It was, I think, those who weren't good enough to be let onto the 432
team that designed the 8086. It would have been better if they had
just taken the 8080 design and doubled most of the registers etc.

Reminds me of the poor old Zilog Z8000.

 

[joseph2k]

In microprogrammable machines, three operands are almost routine,
sometimes four: src A, src B, dest, and next instruction address.

They're fun!

Cheers!
Rich

Maybe i don't remember right but i think that the NS32000 was a two
operand / three operand machine.

 

[Donald]

Rich Grise wrote:



Maybe i don't remember right but i think that the NS32000 was a two
operand / three operand machine.

The Intel 196 family had three operand opcodes.

donald

 

[krw]

John Larkin wrote:


[... CDP1802 ...]
Well, the 8051, at least in its original incantation, isn't much
of a screamer either (12 clocks per op, as well).

There's a big difference between 12 cycles of a 12MHz clock and 12
cycles of a 2 MHZ clock. Besides:

Like I said, there isn't much of a difference.



A = B + C

Compiles to something like 16 instructions if A, B and C are
randomly located in the RAM area.

The 8051 is not so different if A, B, and C are randomly located in
external RAM. I'd never use a HLL on such a beast.


MOV DPTR,#B ; 1
MOVX A,@DPTR ; 2
MOV R5,A ; 3
MOV DPTR,#C ; 4
MOVX A,@DPTR ; 5
ADD A,R5 ; 6
MOV DPTR,#A ; 7
MOVX @DPTR,A ; 8

The 8051 took 8. Now lets see if I can remember the 1802 well enough:

LD #LOW(B) ; 1 Data = low 8 of address
PLO R5 ; 2 Put to low 8
LD #HIGH(B) ; 3 Data = high 8 of address
PHI R5 ; 4 Put to high 8
LD #LOW(C) ; 5
PLO R6 ; 6
LD #HIGH(C) ; 7
PHI R6 ; 8
LD #LOW(A) ; 9
PLO R7 ; 10
LD #HIGH(A) ; 11
PHI R7 ; 12
LDN R5 ; 13 Load what R5 points to
SEX R6 ; 14 Do math with what R6 points to
ADD ; 15 Do the math
STD R7 ; 16 Store where R7 points

The instruction count for the 1802 is double that of the 8051 and with
the slower clock speed, the 1802 takes about a billion times longer to
do the same operation.


Impressive! For a 6800-family gadget, it would be

LDAA A
ADDA B
STAA C

And on the 6803, using "LDAD..." (load double etc) would do it for
word operands, using the A and B accumulators as a 16-bit register.

On a PDP-11, it would have been...

MOV.B A, C or just MOV for word data
ADD.B B, C

and the MSP430 is essentially the same, executing the sequence in
about 400 ns. Both machines allow a choice of relative (relocatable)
or absolute addressing. The rumor is that a few guys invented the
PDP-11 architecture one night in Gordon Bell's basement.

On a 68K, it would be three ops, loadreg/add/store, but you'd have
your choice of byte, word, or long.

There weren't many triple-operand machines around, ever.


John
I actually have worked with a machine that used up to 7 operands for a
single instruction. IIRC the instruction was a repeated move selective
replace using different source and destination indexes, different base
address (with a special interpretation for one), a mask value, replace
value, and iteration count.

Yikes!

Some of the CISC-ier machines, like HP 3000 and Vax and the nearly
forgotten, failed 32-bit Intel chip (what was that called?) had
outrageous instructions, like polynomial eval and hairy string ops,
but that was just tons of microcode so doesn't really count, by my
official decree. The 68332 even has a few, like the linear
interpolation thing and hi/lo limit checks.

John

I think the old intel processor you are talking about the i432 "MicroFlame".
iAPX432.

IIRC it was a four or five chip group for the processor (kinda like a 2901
bit slice machine) and about a 11 by 14 board full of TTL logic (kinda like
the old IBM PC or XT).

Three (monstrous) chips for the CPU, IIRC.

 

[krw]

The Intel 196 family had three operand opcodes.

Three operand opcode machines are fairly common. Any CPU with a
fused multiply-add or dest-src-src instructions will have three
opcodes.