Joining analog and digital ground

[Hammy]

I'm doing an AD9834 board which is a DDS IC. Power is coming from a
5VDC (7805) for analog section and a 3.3Vdc LDO for digital. Both
regulators are off the board. About a two or three inch run of twisted
wire per regulator from the dds board.

The board is two sided with the top being ground and having the AD9834
on it all other components including the 50MHz oscillator are on the
bottom.

My original plan was to join the two grounds on the regulator board,
keeping the two grounds separate on the DDS board. The data sheet says
to join the grounds as close to the AD9834 as possible. They also say
to NOT run the digital ground under the IC but to run the analog
ground under the IC.

I've run the analog ground under the IC. If the grounds are joined as
close to the IC as possible Digital return current would flow under
the IC, according to the data sheet this can couple noise into the IC
die.

Would it not just be better to leave both grounds separate on the DDS
board and bring both grounds back to the regulator board and join them
there at a single point?

 

[Joerg]

I'm doing an AD9834 board which is a DDS IC. Power is coming from a
5VDC (7805) for analog section and a 3.3Vdc LDO for digital. Both
regulators are off the board. About a two or three inch run of twisted
wire per regulator from the dds board.

The board is two sided with the top being ground and having the AD9834
on it all other components including the 50MHz oscillator are on the
bottom.

My original plan was to join the two grounds on the regulator board,
keeping the two grounds separate on the DDS board. The data sheet says
to join the grounds as close to the AD9834 as possible. They also say
to NOT run the digital ground under the IC but to run the analog
ground under the IC.

I've run the analog ground under the IC. If the grounds are joined as
close to the IC as possible Digital return current would flow under
the IC, according to the data sheet this can couple noise into the IC
die.

Would it not just be better to leave both grounds separate on the DDS
board and bring both grounds back to the regulator board and join them
there at a single point?

Just MHO:

Generally, splitting grounds that way is not a good idea. If your
nickname "Hammy" indicates that you operate ham radio gear then it's
even less of a good idea because it can spew EMI and also get upset by
high field strengths.

Since you have such easy access because of only two layers, why not at
least provide plenty of dummy bridges that you can later solder shut or
use 0603 size zero-ohm resistors? Then you can simply try it out without
risk.

I still remember the faces at a client when I soldered a split shut (all
the way, after rattling their nerves with a Dremel) under a bunch of
Analog Devices ADCs despite staunch reminders in its datasheet to split.
Priceless. Tons of noise they had fought for weeks vanished into thin air.

 

[Hammy]

Just MHO:

Generally, splitting grounds that way is not a good idea. If your
nickname "Hammy" indicates that you operate ham radio gear then it's
even less of a good idea because it can spew EMI and also get upset by
high field strengths.

I dont even own a CB.

Joerg you never watched Hammy Hamster when you where a kid .

http://en.wikipedia.org/wiki/Tales_of_the_Riverbank

Since you have such easy access because of only two layers, why not at
least provide plenty of dummy bridges that you can later solder shut or
use 0603 size zero-ohm resistors? Then you can simply try it out without
risk.

I still remember the faces at a client when I soldered a split shut (all
the way, after rattling their nerves with a Dremel) under a bunch of
Analog Devices ADCs despite staunch reminders in its datasheet to split.
Priceless. Tons of noise they had fought for weeks vanished into thin air.

Thanks for the advice thats what I'll do.

 

[Hammy]

No, because then you have different voltage drops between those at the IC
point, so introduce noise between analog and digital ground on the AD9834.

Thats two votes for joinning on the DDS so I'm going to join them on
the DDS board.

Thanks

 

[Hammy]

I dont even own a CB.

Joerg you never watched Hammy Hamster when you where a kid .

http://en.wikipedia.org/wiki/Tales_of_the_Riverbank

Heres a picture of me going on a sunday drive with the little lady.

http://www.hotmoviesale.com/dvds/47351/1/Hammy-Hamster-Volume-4.jpg

 

[Joerg]

I dont even own a CB.

Joerg you never watched Hammy Hamster when you where a kid .

http://en.wikipedia.org/wiki/Tales_of_the_Riverbank

Nope, didn't. I grew up in Europe. But I did watch Archie Bunker

[...]

 

[Joerg]

Heres a picture of me going on a sunday drive with the little lady.

http://www.hotmoviesale.com/dvds/47351/1/Hammy-Hamster-Volume-4.jpg

Ah yes, in a souped-up VW no less

 

[Joerg]

Thats two votes for joinning on the DDS so I'm going to join them on
the DDS board.

But wait until the electoral complaints commission has thoroughly
validated all the ballots ...

 

[Hammy]

If you are not sure of this, first have a look up the manufacturers data
sheet and app notes for the recommended layout. If there isn't one,
email or call application engineering. They can be very helpfull.

We did some work using some ti high speed serdes (internal pll clocks)
links a year or so ago and ended up using power islands around the
device, with separate decoupling cap trees (1nF, 10nF and 100nF) on both
analogue and digital Vcc and Gnd. We haven't had time to find out if
that was overkill by removing some of the parts, but the product passed
emc tests just fine...

Regards,

Chris

I've read everything I could find including there evaluation board.
The layout image is poor quality.

It does look as though they are leaving the grounds separate on the
board. There is one component (fig 8) across the isolation between the
grounds maybe R4 or C15 looking at the component side? I cant make out
any other connection between the grounds.

The board is on page 10 of the pdf. If you can see a connection
between the grounds you have better eyes then me.

http://www.analog.com/static/imported-files/eval_boards/137452056EVAL_AD9834EB.pdf

I'm going to do as Joerg suggested leave it unconnected and then use
jumpers to see what's better.

 

[Joerg]

I've read everything I could find including there evaluation board.
The layout image is poor quality.

It does look as though they are leaving the grounds separate on the
board. There is one component (fig 8) across the isolation between the
grounds maybe R4 or C15 looking at the component side? I cant make out
any other connection between the grounds.

The board is on page 10 of the pdf. If you can see a connection
between the grounds you have better eyes then me.

http://www.analog.com/static/imported-files/eval_boards/137452056EVAL_AD9834EB.pdf

Figure 5 shows a short but the layout isn't readable. Sometimes they'll
let you have the Gerbers, much better.

I'm going to do as Joerg suggested leave it unconnected and then use
jumpers to see what's better.

But you'd have to provide one position every 1/2" or so. Else connecting
at just 2-3 available spots can create loops and make it worse, not
reslting in the performance a full common ground plane would afford.

 

[Rich Grise]

But wait until the electoral complaints commission has thoroughly
validated all the ballots ...

LOL, he in not in Afganistan [/QUOTE]

Florida? <chuckle> ;-)

Cheers!
Rich

 

[John Devereux]

Every board I have designed at work that has A/D or D/A converters (or
both) ALWAYS gets the analog ground and digital ground connected
underneath (or very close) to those ICs.
Other than making sure there is a common potential point close to the
mixed signal ICs, I also arrange the ground planes such that all
digital return currents don't get anywhere near the analog areas of
the board, even if I have to segregate ground planes with 10 mil cut-
outs (in the plane copper) that serpentine over the board.

Tom P.

(not directed at you specifically)

AFAIK the digital ground pin of an ADC does not go to digital ground -
it goes to analog ground!

It is there to conduct the "digital" currents *within the chip package*,
otherwise these would flow down the same bond wire as the chip analog
ground and disturb ADC operation.

See e.g. <http://www.analog.com/static/imported-files/tutorials/MT-031.pdf>

I don't think you want digital ground at all at the ADC itself (but it
can be a good idea to locally buffer the ADC outputs with a buffer
referenced to DGND).

 

[Hammy]

(not directed at you specifically)

AFAIK the digital ground pin of an ADC does not go to digital ground -
it goes to analog ground!

My ADC's are on Analog ground if that was directed to me.

It is there to conduct the "digital" currents *within the chip package*,
otherwise these would flow down the same bond wire as the chip analog
ground and disturb ADC operation.

See e.g. <http://www.analog.com/static/imported-files/tutorials/MT-031.pdf>

Fig.4 seems to be what they are doing on the evaluation board.
Separate ground planes joined only at the power supply.They use
shottkys to keep potential differences between the planes to below
0.3V.

It's a tad confusing in the next example "GROUNDING AND DECOUPLING
MIXED-SIGNAL ICs WITH LOW DIGITAL CURRENTS". They say that the IC DGND
should be joined short trace to the AGND. This to me means one ground
plane? Then they show a buffer referenced to DGND?

This is a quote from the AD9834 data sheet.

"If the AD9834 is in a system where multiple devices require AGND to
DGND connections, the connection should be made at one point only,
establishing a star ground point as close as possible to the AD9834."

For the time being I dont have multiple devices but I will.

Oh well looks like the old trial and error method applies. I was
hopeing to get this right the first time.

 

[John Devereux]

My ADC's are on Analog ground if that was directed to me.


Fig.4 seems to be what they are doing on the evaluation board.
Separate ground planes joined only at the power supply.They use
shottkys to keep potential differences between the planes to below
0.3V.

It's a tad confusing in the next example "GROUNDING AND DECOUPLING
MIXED-SIGNAL ICs WITH LOW DIGITAL CURRENTS". They say that the IC DGND
should be joined short trace to the AGND. This to me means one ground
plane?

Yes, I would say so, around the ADC anyway.


" the AGND and DGND pins should be joined together externally to the
analog ground plane with minimum lead lengths."

Then they show a buffer referenced to DGND?

That is what I was saying below, it is for the case where the ADC output
has to drive long (high capacitance) traces or wires. In this case there
is a current pulse each time that capacitance charges, so a buffer helps
isolate the ADC and referencing the buffer to DGND returns the current
there.

This is a quote from the AD9834 data sheet.

"If the AD9834 is in a system where multiple devices require AGND to
DGND connections, the connection should be made at one point only,
establishing a star ground point as close as possible to the AD9834."

Never used a DDS but I can't see why they would be that different....

 

[Joerg]

My ADC's are on Analog ground if that was directed to me.


Fig.4 seems to be what they are doing on the evaluation board.
Separate ground planes joined only at the power supply.They use
shottkys to keep potential differences between the planes to below
0.3V.

It's a tad confusing in the next example "GROUNDING AND DECOUPLING
MIXED-SIGNAL ICs WITH LOW DIGITAL CURRENTS". They say that the IC DGND
should be joined short trace to the AGND. This to me means one ground
plane? Then they show a buffer referenced to DGND?

This is a quote from the AD9834 data sheet.

"If the AD9834 is in a system where multiple devices require AGND to
DGND connections, the connection should be made at one point only,
establishing a star ground point as close as possible to the AD9834."

That is pretty much guaranteed not to work. OTOH I do have an
appreciation for engineers doing that because it brings me consulting
assignments )

One of those case, four ADCs and one ground connection point, noise
galore, frustration levels at 110%, CEO pacing up and down the lab,
required roughly 22 hours of travel to get there ...

For the time being I dont have multiple devices but I will.

Oh well looks like the old trial and error method applies. I was
hopeing to get this right the first time.

It's perfectly ok to split the grounds and provide narrow jumper points
every half inch or so. Then when the (almost guaranteed) disappointment
sets in it's easy to solder them all shut. Or place zero ohms resistors
if already in production. Occasionally a split ground can work. Maybe.
But you might not pass smog at the EMC lab.

[...]

 

[Joerg]

Every chip maker thinks his chip is the center of the universe. So
every power pin on their eval board has two ferrite beads and four
caps ranging from 100uF to 100pF, and they want analog and digital
grounds that meet only under their chip.

So what you are saying is that chip makers are like politicians?

The fun begins when you have to lay out a non-trivial board with, say,
more than one chip that wants the grounds to meet only under it.

Seriously, I have seen a solution where you had this: DGND, AGDN1,
AGND2, AGND3 ...

The channels were as "quiet" as Candlestick after the 49ers scored.

Sometimes I think that the dumbest interns at some chip manufacturers
are assigned to write the datasheets and do the eval boards.

And eval boards don't have to pass EMI tests.

Which is kind of interesting since many of those are used by hobbyists
at home.

Except for boards with truly isolated channels, I have never done a
board with separate analog and digital grounds. I've never wanted to
have two ground pours at different potentials.

Same here. My only split ground boards were for things like ECG,
intravascular ultrasound, gear for markets where stuff can go kabloiue,
and so on. Where standards usually prescribe the level of isolation and
creepage distances. Even if not, because I always assumed that even
seasoned doctors could panic and apply the defibrillator before
unplugging stuff.

 

[Hammy]

Every chip maker thinks his chip is the center of the universe. So
every power pin on their eval board has two ferrite beads and four
caps ranging from 100uF to 100pF, and they want analog and digital
grounds that meet only under their chip.

The fun begins when you have to lay out a non-trivial board with, say,
more than one chip that wants the grounds to meet only under it.

Sometimes I think that the dumbest interns at some chip manufacturers
are assigned to write the datasheets and do the eval boards.

And eval boards don't have to pass EMI tests.

Except for boards with truly isolated channels, I have never done a
board with separate analog and digital grounds. I've never wanted to
have two ground pours at different potentials.

John

I'm sure you both are right.


I did anticipate the possibility of having to do modifications. I knew
this board is my guinea pig and it was laid out with that in mind.