DVI Receiver -I need a primer

Hi,

I have searched and searched the web but cannot find any links to what I
need to know. In the design of a display project we will be taking the DVI
out of a PC video card. We plan on using the tfp401 DVI receiver chip. We
understand the transmission protocol between the PC and the receiver but...

I cannot seem to find out any timing diagrams on what comes out of the DVI
receiver. I know there is an 8 bit R,G & B buss and some control signals.
If we wanted to create a frame store, say with an FPGA and some SRAM I need
to know the timings. For example how is a new frame defined? What order
do the pixels come out on the pixel buss? Is it Row0,Col0, Row0, Col1...?
Basically what do we need to do to get a frame from the DVI video card into
SRAM frame store? We are looking at 640x480 at the moment.

I'm new to this. VGA was H sync, V sync and line data. Now we are talking
about digital bytes, but we can't seem to figure out how the old H and V
sync relate to the DVI datastream.

If anyone would be so kind as to post some links or further information..

Thanks.

Rob

 

A DVI connector can carry analog and/or digital signals. Assuming you want
the digital information, the electrical interface is compatible with HDMI
IIRC. Perhaps googling for HDMI will help, just ignore the stuff about
HDCP.

 

I do want the digital information. Have searched for HDMI, HDCP, DVI. The
TI tfp401 does have Hsync and Vsync output pins (as other DVI/HDMI chips)
receivers do, but I cannot find any timing diagrams on their use. There
just seem to be much chatter about the actual TMDS transmision methodology
over the copper, but not much about using the actual output from these
receiver chips. Certainly more app notes would be helpful. I hope I don't
have to open up my ACER and scope out what is going on.

Rob