am new to digital electronics and am wondering why the logic for the output of a OR gate is equivalent to a + sign when evaluating an expression..
for example if i was drawing the circuit for the following experession F=A + B...I would use an OR gate with A and B as inputs and F as the output. Yet the truth table for an OR gate is different to that of a Sum output when using a Half Adder to add bits A and B..don't under stand this..
for example if i was drawing the circuit for the following experession F=A + B...I would use an OR gate with A and B as inputs and F as the output. Yet the truth table for an OR gate is different to that of a Sum output when using a Half Adder to add bits A and B..don't under stand this..