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Accurate(ish) frequency measurement

Discussion in 'Electronic Design' started by Michael Brown, Mar 9, 2007.

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  1. I'm playing around with one of my projects at the moment, and what would be
    nice is to have built-in frequency calibration. The project essentially
    involves watching crystals to see how they age (and also is a fun experiment
    as to how stable of an environment - thermal and voltage - I can make).
    Which is probably only somewhat more interesting than watching paint dry to
    most people :) Currently I can do this, but only with an annoying amount of
    external equipment.

    Currently, the board under test has a 4 MHz crystal oscillator as found in
    the LT1016 datasheet. I would like to do fairly accurate frequency
    measurements of this crystal against a rubidium reference 1 PPS source I
    have access to (assumed to have at worst 5E-11 short term stability). I'd
    ideally like to make measurements of the frequency at the 1E-8 level or
    better. Since the board has a microcontroller on it, I would ideally like to
    simply plug in the 1 PPS source and read out a frequency through a serial

    The simple method - counting cycles - would sort of work. If I count the
    output of the xtal oscillator for about 25 seconds I should get an error of
    1 part in 10^8. But I'd like to make the measurement faster (for 'I doubt I
    can hold everything stable for that long' reasons and because faster =
    better) and ideally not simply limited in accuracy to how long I wait.

    My plan is to make a slight variant on a TAC. The number of full XTAL cycles
    in between the reference rising edges is obviously easy to measure. To
    measure the part cycles, I was going to use the discharge time of a
    capacitor. For the final part cycle: initially prepare the capacitor to ~1V,
    start charging it (+5V -> resistor -> capacitor -> GND) on the rising edge
    of the 1 PPS source, keep charging until the rising edge of the 4 MHz clock,
    then discharge it through a much bigger resistor and count how many 4 MHz
    cycles occur until it hits ~0.8V. There's a few complications to avoid
    dropping or collecting extra cycles, but that's the basic idea. Also,
    there's obviously non-linearity problems here but nothing a bit of
    microcontroller time can't fix. A similar method will be used for measuring
    the start partial cycle.

    Since this is living on a double-sided PCB, using a much higher frequency
    clock to measure things more accurately isn't too feasable. Another
    alternative would be to simply go out and buy a nice TDC chip from somewhere
    .... unfortunately obtaining one or two of these appears to be either
    impossible or extremely expensive - neither of which are helped by the fact
    that I'm in Australia.

    The questions (finally!) are
    1) Is this the sensible way to do it?
    2) Slew rate and switching delay for the capacitor charging (and to a letter
    degree, the discharging) circuit is obviously important. From a back of the
    envelope calculation even a BC109 seems to be able to do the job, but that
    seems too easy. A MOSFET + driver is mess that I'd rather avoid.
    3) Any nasty hidden surprises in these types of circuits that I should keep
    an eye out for when designing it?
  2. You are in closed loop situation. Frequency IS 1/time so a reliable and
    accurate reference to one of them is needed. It is obtained either by
    measured certification of the source or by long term statistical

    Good hunting

    Slack user from Ulladulla.
  3. Capacitors have a nasty habit, to arrive at charging/discharging level
    to 1% accuracy you need ~ 3RC (time constants) or precise and fast

  4. jure

    jure Guest

    Sounds interesting Michael ,

    although you have to decide for yourself if it is worth the exercise.
    You could improve better that 100x your single shot precision in 1
    sec, using the TAC interpolators.
    Certainly it may be quite a learning experience that could be applied
    to other fields....

    So, the situation is:

    a) there is an accurate 1 Hz gate signal.
    b) there is an unknown clock of frequency close to 4 MHz.
    c) an interpolator will find Delta_T1 = the time from the active
    edge of the gate to the next active edge of the unknown clock.
    ( Delta_T1 is in your case less than 25 ns )
    d) a counter will count the integer number N of clock cycles
    between the first active clock edge after the first active edge of the
    and the first active edge of the clock after the last active
    edge of the gate.
    e) a second interpolator will find Delta_T2 = the time from the
    2nd active edge of the gate to the next active edge of the unknown
    ( Delta_T2 is in your case less than 25 ns )

    Note : here your case is a little easier than the more
    general solution:
    you stop the second interpolator after the counter
    reaches N = 4 000 000

    f) compute the time it took to run N = 4 000 000 complete cycles

    T = 1 s + Delta_T2 - Delta_T1

    then , the 1s averaged unknown frequency is: Fx = 4 000
    000 / T

    Extra Notes:

    1) the interpolator is a gated constant current source charging a
    capacitor ( => linear ramp voltage on C ), followed by a sample and
    hold, and an ADC.
    2) there could be one single interpolator , given that there is 1s
    between its use for the gate start and gate stop ( and you have 1
    second to: integrate , hold, convert , read ADC , reset ).
    3) the system may be pipelined to get one frequency reading per
    second, but you will need two interpolators.
    4) I would stay with one interpolator, so that you will have to
    calibrate only one of them , not two.
    5) the interpolator(s) have to be calibrated so that the addition
    above is meaningful, (how many ADC counts per Fx period are there ?)
    5) all the logic , the counter and the state machine controlling the
    system may be implemented in a fast CPLD.
    6) the scheme presented above assumes that the unknown frequency is 4
    MHz +/- 1Hz ( ie +/- one count in 1 s),
    if not you could change the state machine so that the interpolators
    span 2 or more clock cycles, then change everything else to match)

    timing diagram ( see with fixed point courier ):

    __________________... 1s ....
    1s Gate signal | |
    ______| ....____|

    Fx Clock |
    ..___| ..._|

    ->| |<- DT1 ->| |<-

    Clock Edge # 0 Clock
    Edge # N-1

    Thanks , Jure Z.
  5. jure

    jure Guest


    after one more minute of thinking,

    the statement :

    could be corrected adding that using one interpolator and producing
    one reading per second is possible by using the Delta2 from the
    previous measurement as Delta1 of the current measurement.

    Jure Z.
  6. jure

    jure Guest

    noticed a mistake : wherever I said 25 ns , please read 250ns.

    Jure Z.
  7. jure wrote:
    [snip lots of good stuff]
    Ahh, nice! Didn't think of that. I was planning to do the interpolator
    calibration prior to the frequency measurement, but for a "continuous"
    scheme like this it'd also work quite well to do it in the part of the 1
    second interval that's not used for the measurement.

    The approach I'm working with now is to simply latch the output of a counter
    (fed with the 4 MHz clock) on each 1 PPS rising edge (more or less, with a
    bit of logic to handle boundary cases) and then use the interpolator as you
    described. With a bit more thought, I think (as you suggest) an ADC such as
    the ADCS7476 will work better than the quasi-ADC that I was using (on the
    hunch that since I already had most of an ADC there it would be
    better/easier). The microcontroller then handles the rest (counter
    wrap-around, etc).

    A question regarding the interpolator itself ... short term (5-second-ish)
    stability-wise, would a constant voltage + resistor be better or worse than
    a constant-current source? Stable voltage references are a dime a dozen
    nowadays, but I'm not sure how well they'd work if you try running them in
    constant current mode. The nonlinearity of using a constant voltage is not a
    huge problem since it can be cleaned up by the microcontroller.

    I'm still trying to decide on whether to go with discretes or a CPLD.
    Unfortunately, CPLDs are only available down here in Australia with extreme
    markups - the part I'm considering is a XC9536XL-5PC44 (one of the cheapest
    flash-based CPLDs that I could find), which can be bought in single-piece
    quantities from dozens of US places for ~$1.50, yet retails here for 10
    times that. I can buy a LOT of 74AC discretes for $15. Additionally, I can't
    find any CPLDs that can output 5V levels, which is what it's interfacing
    with uses. Not impossible to deal with, just annoying, and requires yet
    another voltage regulator to power it, or reconfiguration of the rest of the
    circuit to 3.3V levels. Obviously, I'm currently leaning quite strongly
    towards discretes ...
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