68hc11 and z85230

[giovanni]

Hi all,

has anyone tried to successfully connect the motorola 68hc11 to the
zilog z85230?
I am trying to make them work together but it seems I am able to read
but not to write.

data from 68hc11 are directly connected to the data lines on the
z85230. Control signals rd and wr come from 68hc11. chip enable and d/c
come from a PLD.

I am thinking about delaying the write signal, in order to make it fit
the z85230 timing constraints: could this help?

Thanks in advance for your time and considerations.
Giovanni

 

[James Beck]

Hi all,

has anyone tried to successfully connect the motorola 68hc11 to the
zilog z85230?
I am trying to make them work together but it seems I am able to read
but not to write.

data from 68hc11 are directly connected to the data lines on the
z85230. Control signals rd and wr come from 68hc11. chip enable and d/c
come from a PLD.

I am thinking about delaying the write signal, in order to make it fit
the z85230 timing constraints: could this help?

Thanks in advance for your time and considerations.
Giovanni

I have no clue what a z85230 is, but first and foremost is to make sure
you make the /RD and /WR using the HC11 RW line and the HC11 E clock,
then any chip selects need to be ANDed with the E clock.

In other words :
/RD = !(RW & E)
/WR = !(!RW & E)
All address decoding needs to be ANDed with the E clock also.

I usually use a small PLD to create the /RD and /WR signals along with
the inverted reset some of the peripherals need and any odd address
decoding that is needed.

Hope this helps

Jim