What do you want to delay?
A fairly simple solution would be something like this:
View attachment 38546
With the appropriate choice of R and C, this will delay both rising and falling edges of a logic signal. However, as the edges get closer together, the delay will decrease, and at some point the output will no longer change.
The maximum delay is given by (approx) t = 1.1 RC
Do not use values of R < 1kΩ as the impedance of the gate will then become a large factor.
1MΩ and 0.1μF will give you approx 110ms