VLSI layout layer description

[frank]

hello,

I as wondering if anyone could direct to me to any good links
describing the different layers that are used to perform vlsi design.
I am familiar with most of them, but I could not find anywhere what
the NFIELD layer is. It is not NWELL, but it mirrors it in all the
places where there is NWELL. I suspect it is suppose to indicate that
the location of lightly doped n. Can anyone confirm this? How is it
different with NWELL?

P.S The technology is: for xfab 0.35um XC035LV cmos. See document :
http://www.xfab.com/xfab/frontend/img_db/dl_mg_1064582343.pdf

page. 3

Thx.
-Frank

 

[wally]

hello,

I as wondering if anyone could direct to me to any good links
describing the different layers that are used to perform vlsi design.
I am familiar with most of them, but I could not find anywhere what
the NFIELD layer is. It is not NWELL, but it mirrors it in all the
places where there is NWELL. I suspect it is suppose to indicate that
the location of lightly doped n. Can anyone confirm this? How is it
different with NWELL?

P.S The technology is: for xfab 0.35um XC035LV cmos. See document :
http://www.xfab.com/xfab/frontend/img_db/dl_mg_1064582343.pdf

page. 3

Thx.
-Frank

problem is Frank that different foundries will give the same layers
different names.

eg, i have seen gate conductor called various different names : poly1,
GC, gateC, etc..

also, lots of layers exist which you do not actually physically draw, ie
they are generated automatically from the drawn layers.

The foundary you are using will have all the docs you need.