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VLSI question regarding parasitic-extracted layout

Discussion in 'Electronic Design' started by Ant_Magma, May 2, 2006.

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  1. Ant_Magma

    Ant_Magma Guest

    Hi, i'm not sure if this workgroups is suitable for VLSI questions but
    since this is the closest i managed to found so i'm going to post it
    here, hope you guys don't mind.

    I'm working on a simple project of building a 6T SRAM cell. In the
    question, the a section of the report requires "Simulation results of
    the parasitic-extracted layout". Unfortunately, since my instructor is
    not around for a few days i have no one to ask so i was hoping if
    anyone here can explain to me what is it? And how do i obtain it?

    I'm using the layout tool called MAGIC.

    Thx guys....
     
  2. Jim Thompson

    Jim Thompson Guest

    I don't know how to do it, but your layout tool can EXTRACT a netlist
    from your layout that includes the parasitic capacitances (and
    sometimes metalization resistances).

    ...Jim Thompson
     
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