R
Rajesh T
- Jan 1, 1970
- 0
VLSI Design 2004
The Seventeenth International Conference on VLSI Design
and
The Third International Conference on Embedded Systems Design
January 5-9, 2004,
Renaissance Mumbai Hotel and Convention Centre
Mumbai, India.
(http://www.ee.iitb.ac.in/~vlsi2004)
********************************************************************
The 17th International Conference on VLSI Design will be held
jointly with the 3rd International Conference on Embedded Systems
Design in Mumbai, India, during January 5-9, 2004. It will bring
together eminent researchers, academicians, and engineers working
in VLSI design and embedded systems from all over the world. This
is a leading and prestigious international conference held annually
in India, with a very strong technical program. It offers a unique
opportunity to participants to meet researchers and practicing
engineers in the areas of VLSI and embedded systems from both within
the country and abroad. A major attraction of VLSI Design 2004 is
that for the first time, as many as 35 Invited Talks will be
delivered during the conference by eminent speakers of international
repute on a wide range of topics. The list of speakers includes
Fellows of IEEE, Fellows of ACM, Distinguished Lecturers of the
IEEE EDS and CAS societies, Distinguished Fellows from industry,
the main architect of Verilog, the creator of RT Linux, the author
of Esterel, the inventor of the world's smallest web server, and
other eminent experts in areas ranging from VLSI Design to Device
Technology.
The VLSI Design conference is well known for its highly successful
series of tutorials. VLSI Design 2004 and ICES-3 will feature eight
tutorials on a wide variety of topics ranging from device technology
to system design. The tutorials will be conducted by leading groups
from across the world both from industry and academia. The tutorials
are expected to be of great benefit to students, researchers, and
practicing engineers working in the broad areas of VLSI design and
embedded systems.
A large number of research papers will be presented during the three
days of the conference with representation from industry, academia,
and R and D organizations. VLSI Design 2004 and ICES-3 has attracted
328 papers of very high quality out of which 135 papers have been
accepted for presentation at the conference.
An Industry Design session is also being organized as a part of
VLSI Design 2004 and ICES-3 where finished designs from industry
participants will be discussed, offering a great opportunity for
industries to interact with each other and exhibit their
achievements. Exhibit stalls and presentations from various
industries will further enhance interaction with industry
participants. A special Research Scholars forum is also being
organized where research scholars will get an opportunity to
display their work and obtain valuable feedback from the
conference participants.
VLSI Design 2004 and ICES-3 is being organized by the Indian
Institute of Technology, Bombay under the auspices of the VLSI
Society of India, with support from the Ministry of Communication
and Information Technology. The conference is held with technical
co-sponsorship from IEEE Electron Devices Society and IEEE Circuits
and Systems Society and in cooperation with ACM-SIGDA. Local
support is provided by IEEE Bombay Section and IEEE AP/ED Bombay
Chapter.
RESEARCH PAPERS in the following areas will be presented:
* Gigascale design methodology
* Embedded systems-hardware/software co-design
* FPGA-based design
* Analog-digital mixed signal SOC
* Concurrent package and board design
* CMOS and interconnect reliability
* Gigascale integrated circuit manufacturing
* Digital imaging
* DSP design
* High-level synthesis
* Logic synthesis
* ASIC design
* Core-based systems
* Reconfigurable hardware design
* Asynchronous Design
* Interconnect aware design
* All aspects of test and DFT
* Formal Verification
* Processor design
* Low-power design
* Mixed signal and analog design
* RF design and modeling
* Performance-driven design
* Physical design
* Programmable devices
* Advances in Memory Design
* Simulation and standards
* Applications:
DSP/Communication/Encryption/Security/Compression etc.
* Issues in deep-submicron VLSI
* Impact of process technology on design
* TCAD: Technology modeling and Device Design and simulation
* Compact modeling
TUTORIALS:
* Samar K. Saha, Silicon Storage Technology, Inc., USA,
"Technology CAD: Technology modeling, device design and simulation"
* S. Sur-Kolay, B. B. Bhattacharya, ISI Kolkata
P. S. Dasgupta, IIM Kolkata,
S. T. Zachariah, Intel, Bangalore
"Physical Design Trends and Layout-based Fault Modeling"
* I. Ghosh, M. Prasad, and R. Mukherjee,
Fujitsu Labs of America, USA,
"High Level Design Validation: Current Practices and Future
Directions"
* Krithi Ramamritham, Kavi Arya, IIT Bombay,
G. Fohler, Malardalen University, Sweden,
"System Software for Embedded Applications"
* Siva G. Narendra, V. Erraguntla, J. Tschanz, and
N. Borkar, Intel, USA,
"Design challenges in sub-100nm high performance microprocessors"
* P. A. Beerel, Fulcrum Microsystems,
J. Cortadella, Universitat Politecnica de Catalunya, Spain,
A. Kondratyev, Cadence Design Systems,
"Bridging the gap between asynchronous design and designers"
* J. Rajski and N. Mukherjee, Mentor Graphics, USA
"Embedded Test For Low Cost Manufacturing"
* G. Berry and L. Blanc, Esterel Technologies, USA
"Synchronous Methodology for Designing Hardware, Software and Mixed
Embedded Systems"
INVITED TALKS:
* H. Iwai, Tokyo Institute of Technology, Japan
(Advances in CMOS technology in sub 90 nm nodes, PLENARY TALK)
* Paul G.A.Jespers, Catholic University, Leuven
(High-speed integrated converters, PLENARY TALK)
* D. Monticelli, National Semiconductor Corp, USA
(Power management in analog systems, PLENARY TALK)
* P. Moorby, Synopsys, USA
(Design for verfication with system Verilog, PLENARY TALK)
* Srinivas Raman, Intel, India
(Giga Transistor Microprocessors in Platforms of the Future,
PLENARY TALK)
* Bill Witowsky, Texas Instruments, USA
(Voice over internet issues, BANQUET SPEECH)
* Sanjive Agarwala, Texas Instruments, USA
(An 800MHz System-on-Chip for wireless
infrastructure applications)
* Vishwani Agrawal, Auburn University, USA
(A tutorial on the emerging nanotechnology devices)
* N. Balram, National Semiconductor Corp., USA
(Advanced LCD timing controller IC)
* G. Berry, Esterel Technologies, USA
(Embedded Systems)
* A. Chandrakasan, MIT, USA
(Microsensors design considerations)
* Chandrashekhar, CEERI, India
(Application-specific instruction set processors:
Redefining hardware-software boundary)
* Cor Claeys, IMEC, Belgium
(Technological challenges of advanced CMOS processing
and their impact on design aspects)
* B. Courtois/S.Mir, TIMA Laboratory, Grenoble, France
(On-chip testing of embedded transducers)
* Sujit Dey, University of California, San Diego, USA
(Configurable platforms: an efficient alternative to ASIC's)
* Kaushik Dutta/P.Das, Interra systems, India
(Assertion based verification using HDVL)
* M. Fujita, University of Tokyo, Japan
(Formal Verification of C language based VLSI design)
* H. Gossner, Infineon, Germany
(ESD issues in deep submicron transistors)
* Rajat Gupta, Cypress semiconductors, India
(Digital design: the components of a new paradigm)
* R.Harjani, University of Minnesota, USA
(RF physical layer issues for UWB systems)
* M. Mehendale, Texas Instruments, India
(Design challenges for embedded real-time DSP SOC's)
* N. S. Nagraj, Texas Instruments, USA
(Interconnect models)
* M. K. Radhakrishnan, NUS, Singapore
(Device reliability issues)
* A. Raghunathan, Princeton University/NEC, USA
(Embedded systems security: tamper resistant architectures)
* C. P. Ravikumar, Texas Instruments, India
(Multiprocessor architectures for embedded SOC)
* K. Ramirez-Angelo, New Mexico State University, USA
(Low-Voltage analog CMOS circuits)
* Kaushik Roy, Purdue University, USA
(Low-power design)
* J. Roychowdhury, University of Minnesota, USA
(Macro Modeling for mixed-signal systems)
* S. Sapatnekar, University of Minnesota, USA
(High-performance power grid for nanometer technology)
* Satnam Singh, Xilinx Research Labs, USA
(Novel reconfigurable systems)
* H. Shrikumar, Enablery Inc, USA
(Tiniest Web Server)
* R. Sridhar, SUNY, Buffalo
(Clocking and synchronization in SOC)
* Ahmed Tewfik, University of Minnesota, USA
(UWB system design)
* Wayne Wolf, Princeton University, USA
(Networks on chips)
* V. Yodaiken, FSM labs, USA
(RT Linux)
FELLOWSHIPS
The Steering Committee will award fellowships, based on need
and merit, to partially cover expenses of students and faculty
members from India. Applications must be submitted by October 15,
2003, using the conference website.
IMPORTANT DATES
Advance Registration deadline Dec 16, 2003
Tutorial dates: Jan 5-6, 2004
(venue: IIT Bombay)
Conference dates: Jan 7-9, 2004
(venue: Renaissance Mumbai Hotel
and Convention Centre)
------------------------------------------------------------------------
Sponsors
Platinum Sponsors: Tata Consultancy Services, India.
Gold Sponsors:
Intel, India
Natsem India Designs, India
Synopsys, India
Texas Instruments, India
Silver Sponsors:
Cadence, India
Conexant, India
Cypress semiconductors, India
Infineon, India
------------------------------------------------------------------------
Conference Travel Agent and Event Manager: Thomas Cook, India
For more information, visit
http://www.ee.iitb.ac.in/~vlsi2004
e mail contact:
[email protected]
- Mahesh Patil, Vamsi Srikantam
Publicity Chairs, VLSI Design-2004
(please visit the web site for instructions to register)
Regards
Rajesh
PS: pls do not reply to this mail
The Seventeenth International Conference on VLSI Design
and
The Third International Conference on Embedded Systems Design
January 5-9, 2004,
Renaissance Mumbai Hotel and Convention Centre
Mumbai, India.
(http://www.ee.iitb.ac.in/~vlsi2004)
********************************************************************
The 17th International Conference on VLSI Design will be held
jointly with the 3rd International Conference on Embedded Systems
Design in Mumbai, India, during January 5-9, 2004. It will bring
together eminent researchers, academicians, and engineers working
in VLSI design and embedded systems from all over the world. This
is a leading and prestigious international conference held annually
in India, with a very strong technical program. It offers a unique
opportunity to participants to meet researchers and practicing
engineers in the areas of VLSI and embedded systems from both within
the country and abroad. A major attraction of VLSI Design 2004 is
that for the first time, as many as 35 Invited Talks will be
delivered during the conference by eminent speakers of international
repute on a wide range of topics. The list of speakers includes
Fellows of IEEE, Fellows of ACM, Distinguished Lecturers of the
IEEE EDS and CAS societies, Distinguished Fellows from industry,
the main architect of Verilog, the creator of RT Linux, the author
of Esterel, the inventor of the world's smallest web server, and
other eminent experts in areas ranging from VLSI Design to Device
Technology.
The VLSI Design conference is well known for its highly successful
series of tutorials. VLSI Design 2004 and ICES-3 will feature eight
tutorials on a wide variety of topics ranging from device technology
to system design. The tutorials will be conducted by leading groups
from across the world both from industry and academia. The tutorials
are expected to be of great benefit to students, researchers, and
practicing engineers working in the broad areas of VLSI design and
embedded systems.
A large number of research papers will be presented during the three
days of the conference with representation from industry, academia,
and R and D organizations. VLSI Design 2004 and ICES-3 has attracted
328 papers of very high quality out of which 135 papers have been
accepted for presentation at the conference.
An Industry Design session is also being organized as a part of
VLSI Design 2004 and ICES-3 where finished designs from industry
participants will be discussed, offering a great opportunity for
industries to interact with each other and exhibit their
achievements. Exhibit stalls and presentations from various
industries will further enhance interaction with industry
participants. A special Research Scholars forum is also being
organized where research scholars will get an opportunity to
display their work and obtain valuable feedback from the
conference participants.
VLSI Design 2004 and ICES-3 is being organized by the Indian
Institute of Technology, Bombay under the auspices of the VLSI
Society of India, with support from the Ministry of Communication
and Information Technology. The conference is held with technical
co-sponsorship from IEEE Electron Devices Society and IEEE Circuits
and Systems Society and in cooperation with ACM-SIGDA. Local
support is provided by IEEE Bombay Section and IEEE AP/ED Bombay
Chapter.
RESEARCH PAPERS in the following areas will be presented:
* Gigascale design methodology
* Embedded systems-hardware/software co-design
* FPGA-based design
* Analog-digital mixed signal SOC
* Concurrent package and board design
* CMOS and interconnect reliability
* Gigascale integrated circuit manufacturing
* Digital imaging
* DSP design
* High-level synthesis
* Logic synthesis
* ASIC design
* Core-based systems
* Reconfigurable hardware design
* Asynchronous Design
* Interconnect aware design
* All aspects of test and DFT
* Formal Verification
* Processor design
* Low-power design
* Mixed signal and analog design
* RF design and modeling
* Performance-driven design
* Physical design
* Programmable devices
* Advances in Memory Design
* Simulation and standards
* Applications:
DSP/Communication/Encryption/Security/Compression etc.
* Issues in deep-submicron VLSI
* Impact of process technology on design
* TCAD: Technology modeling and Device Design and simulation
* Compact modeling
TUTORIALS:
* Samar K. Saha, Silicon Storage Technology, Inc., USA,
"Technology CAD: Technology modeling, device design and simulation"
* S. Sur-Kolay, B. B. Bhattacharya, ISI Kolkata
P. S. Dasgupta, IIM Kolkata,
S. T. Zachariah, Intel, Bangalore
"Physical Design Trends and Layout-based Fault Modeling"
* I. Ghosh, M. Prasad, and R. Mukherjee,
Fujitsu Labs of America, USA,
"High Level Design Validation: Current Practices and Future
Directions"
* Krithi Ramamritham, Kavi Arya, IIT Bombay,
G. Fohler, Malardalen University, Sweden,
"System Software for Embedded Applications"
* Siva G. Narendra, V. Erraguntla, J. Tschanz, and
N. Borkar, Intel, USA,
"Design challenges in sub-100nm high performance microprocessors"
* P. A. Beerel, Fulcrum Microsystems,
J. Cortadella, Universitat Politecnica de Catalunya, Spain,
A. Kondratyev, Cadence Design Systems,
"Bridging the gap between asynchronous design and designers"
* J. Rajski and N. Mukherjee, Mentor Graphics, USA
"Embedded Test For Low Cost Manufacturing"
* G. Berry and L. Blanc, Esterel Technologies, USA
"Synchronous Methodology for Designing Hardware, Software and Mixed
Embedded Systems"
INVITED TALKS:
* H. Iwai, Tokyo Institute of Technology, Japan
(Advances in CMOS technology in sub 90 nm nodes, PLENARY TALK)
* Paul G.A.Jespers, Catholic University, Leuven
(High-speed integrated converters, PLENARY TALK)
* D. Monticelli, National Semiconductor Corp, USA
(Power management in analog systems, PLENARY TALK)
* P. Moorby, Synopsys, USA
(Design for verfication with system Verilog, PLENARY TALK)
* Srinivas Raman, Intel, India
(Giga Transistor Microprocessors in Platforms of the Future,
PLENARY TALK)
* Bill Witowsky, Texas Instruments, USA
(Voice over internet issues, BANQUET SPEECH)
* Sanjive Agarwala, Texas Instruments, USA
(An 800MHz System-on-Chip for wireless
infrastructure applications)
* Vishwani Agrawal, Auburn University, USA
(A tutorial on the emerging nanotechnology devices)
* N. Balram, National Semiconductor Corp., USA
(Advanced LCD timing controller IC)
* G. Berry, Esterel Technologies, USA
(Embedded Systems)
* A. Chandrakasan, MIT, USA
(Microsensors design considerations)
* Chandrashekhar, CEERI, India
(Application-specific instruction set processors:
Redefining hardware-software boundary)
* Cor Claeys, IMEC, Belgium
(Technological challenges of advanced CMOS processing
and their impact on design aspects)
* B. Courtois/S.Mir, TIMA Laboratory, Grenoble, France
(On-chip testing of embedded transducers)
* Sujit Dey, University of California, San Diego, USA
(Configurable platforms: an efficient alternative to ASIC's)
* Kaushik Dutta/P.Das, Interra systems, India
(Assertion based verification using HDVL)
* M. Fujita, University of Tokyo, Japan
(Formal Verification of C language based VLSI design)
* H. Gossner, Infineon, Germany
(ESD issues in deep submicron transistors)
* Rajat Gupta, Cypress semiconductors, India
(Digital design: the components of a new paradigm)
* R.Harjani, University of Minnesota, USA
(RF physical layer issues for UWB systems)
* M. Mehendale, Texas Instruments, India
(Design challenges for embedded real-time DSP SOC's)
* N. S. Nagraj, Texas Instruments, USA
(Interconnect models)
* M. K. Radhakrishnan, NUS, Singapore
(Device reliability issues)
* A. Raghunathan, Princeton University/NEC, USA
(Embedded systems security: tamper resistant architectures)
* C. P. Ravikumar, Texas Instruments, India
(Multiprocessor architectures for embedded SOC)
* K. Ramirez-Angelo, New Mexico State University, USA
(Low-Voltage analog CMOS circuits)
* Kaushik Roy, Purdue University, USA
(Low-power design)
* J. Roychowdhury, University of Minnesota, USA
(Macro Modeling for mixed-signal systems)
* S. Sapatnekar, University of Minnesota, USA
(High-performance power grid for nanometer technology)
* Satnam Singh, Xilinx Research Labs, USA
(Novel reconfigurable systems)
* H. Shrikumar, Enablery Inc, USA
(Tiniest Web Server)
* R. Sridhar, SUNY, Buffalo
(Clocking and synchronization in SOC)
* Ahmed Tewfik, University of Minnesota, USA
(UWB system design)
* Wayne Wolf, Princeton University, USA
(Networks on chips)
* V. Yodaiken, FSM labs, USA
(RT Linux)
FELLOWSHIPS
The Steering Committee will award fellowships, based on need
and merit, to partially cover expenses of students and faculty
members from India. Applications must be submitted by October 15,
2003, using the conference website.
IMPORTANT DATES
Advance Registration deadline Dec 16, 2003
Tutorial dates: Jan 5-6, 2004
(venue: IIT Bombay)
Conference dates: Jan 7-9, 2004
(venue: Renaissance Mumbai Hotel
and Convention Centre)
------------------------------------------------------------------------
Sponsors
Platinum Sponsors: Tata Consultancy Services, India.
Gold Sponsors:
Intel, India
Natsem India Designs, India
Synopsys, India
Texas Instruments, India
Silver Sponsors:
Cadence, India
Conexant, India
Cypress semiconductors, India
Infineon, India
------------------------------------------------------------------------
Conference Travel Agent and Event Manager: Thomas Cook, India
For more information, visit
http://www.ee.iitb.ac.in/~vlsi2004
e mail contact:
[email protected]
- Mahesh Patil, Vamsi Srikantam
Publicity Chairs, VLSI Design-2004
(please visit the web site for instructions to register)
Regards
Rajesh
PS: pls do not reply to this mail
