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type of fault in vlsi circuit ?

Discussion in 'General Electronics Discussion' started by vead, May 30, 2014.

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  1. vead

    vead

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    Nov 27, 2011
    How many type of fault can be occur in VlSI circuit ?

    my effort
    physical fault during manufacturing process
    circuit fault during interconnection
    packing fault

    Q1 does anyone know another fault ?
    Q2 what is fault model and why does we need in vlsi circuit?
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

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    Nov 17, 2011
    Some that come to mind:
    • fpga: single event upset (Google)
    • operatig under wrong conditins (overvoltage, overtemperature...)
    • electromigration (Google)
    • metastable states (Google)
    • faulty design
    • ...
     
  3. vead

    vead

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    Nov 27, 2011
    you did not understand actually what I am asking

    when we make chip It may be work or it may be fail due to some fault
    chip may be fail due to fabrication process
    chip may be fail due to circuit connection
    chip may be fail due to packing

    how we will detect fault in chip and what is fault model in vlsi system
     
  4. Harald Kapp

    Harald Kapp Moderator Moderator

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    Nov 17, 2011
    A typical fault model ist the stuck-at fault. One assumes that a net is either permanently high (stuck-at-1) or low (stuck-at-0). One simulates the chip with and without fault and compares the results. If the results are different, the fault can be detected. If the results are the same, the fault is not detetcted by this test pattern and a new test pattern is created. Creating good test patterns is a science in itself.
    There are other types of stuck-at faults (stuck open...) but they are increasingly difficult to simulate. Often the simple stuck-at-1/0 model gives satisfying results.
    Large VLSI circuits also contain additional test circuits. E.g. a ring oscillator , here the frequency of the oscillator is a measure of the quality of the manufacturing process. Or test multiplexers that are activated to gain acces to internal circuit nodes that are otherwise not available for testing (an interesting note on the side: sometimes special test points that need to be accessed after a chip has been assembled are connected to pins which are labeled NC - not connected. This is typical e.g. for voltage references for trimming purposes. One should really not connect these pins to any external circuit because the operation of the chip can be unpredictable. But I stray...)
     
  5. vead

    vead

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    Nov 27, 2011
    I am little bit confused about fault , fault model , and testing

    fault - component fault , circuit fault
    fault model - delay fault, stuck at fault
    testing - testing for component , testing for circuit connection

    can you explain little bit all three things in vlsi system
     
  6. Harald Kapp

    Harald Kapp Moderator Moderator

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    Nov 17, 2011
    I don't understand waht you don't understand:

    fault - the actual fault, whatever went wrong durcing production
    fault model - a simplified model how a real fault will influcence the operation of a circuit
    testing - find out if and where a fault is in the real product

    There is no real difference for these things between a simple logic circuit and a huge VLSI circuit - only the size of the circuit.
     
  7. vead

    vead

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    Nov 27, 2011
    VLSI design are automated

    customer requirement
    specification
    functional design (by using hardware description language )
    digital design (using gate level model )
    circuit level (using gate are implement using transistor )
    layout design
    fabrication process ( layout is convert into real chip )
    chip manufactured

    suppose this chip is not working
    how we will determine fault in chip
     
  8. Harald Kapp

    Harald Kapp Moderator Moderator

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    Nov 17, 2011
    No. There are a lot of tools to partly automate routine work and to assist the developer. But in the end, it is still a human developer who has to interpret the requirements and translate them into something the VLSI design tools can "understand".

    BY testing, as I explained before (see especially post #4)
     
  9. vead

    vead

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    Nov 27, 2011
    I understood testing is used to determine fault in chip
    fault may be occur during fabrication , during connection , during packaging

    Q1 If fault is present in component , which testing method we will use to detect fault ?
    Q2If fault is present in interconnection , which testing method we will use to detect fault ?
    Q3 If fault is know, can we recover fault in chip ?
     
  10. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    A1 Your testing of functionality should show up errors in the functionality. Faults which do not change the functionality may not be significant.

    A2 The same testing

    A3 No, unless you have built something into the design to allow for this.
     
  11. vead

    vead

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    Nov 27, 2011
    Q1 when does we do testing after manufacture or before start up circuit

    Q2 chop is not working we don't know what is fault
    what is process to determine fault
    I mean which method we will use step by step ?

    1. path sensitization
    2. D algorithm
    3. full scan & partial scan
    4 built in self test
     
  12. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    I presume you would do testing at all stages.

    The chips would be tested on the wafer before they're even split up into individual pieces.

    Then there would be testing after they have the bonding wires attached (probably after they're encapsulated)

    If they require programming then perhaps you test them after programming.

    And you would certainly run some tests after the device is built.

    The method you use could be any or all of the methods you propose. There is no magic bullet.

    You need to determine if the fault is due to

    1. Design
    2. Manufacture
    3. Programming
    4. Something else

    Your simulations should take care of (1), bu note that simulations are not perfect. For errors in manufacture, this will either be systematic (failure of (say) the mask) that might be determined only by examination of the chip under a microscope, or they might be random (in which case only some devices will be affected, and the fauults are likely to differ). If it's a fault in programming then you might have a trivial "hello world" application that you could use to verify that you have the basics working, and beyond that you're into a typical software debugging cycle. If it's (4) (maybe damage due to wrong supply rail, poor anti-static handling, etc) then you need to determine how it's happening and to fix that.
     
  13. vead

    vead

    473
    14
    Nov 27, 2011
    VLSI design

    customer requirement
    specification
    functional design at register transfer level using some hardware language (verilog , vhdl )
    fault or error detect by functional simulation

    next step logic design
    functions are decompose into gate level
    logic simulation
    error is detect by truth table, boolean equation method

    next circuit design

    logic circuit made with cmos transistor
    circuit simulation

    layout design geometric pattern

    layout verification

    fabrication process ( layout is convert into real chip )

    chip manufactured

    next we will test the chip to ensure that chip is working correctly or incorrectly

    In vlsi design we have detected all error by simulation
    In manufacturing we are testing wafer

    I am confused .I don't understand at which level we will use following method

    1. path sensitization
    2. D algorithm
    3. full scan & partial scan
    4 built in self test
     
  14. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    Vead, it's a simple 2 step process.

    1. Find out what's wrong
    2. Fix it.
    With your question finally answered we can close this thread.
     
    vead likes this.
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