Verifying Chip Capacitors

[rickman]

I build picosecond stuff that works. Do you?

That is exactly the sort of stuff that makes you sound like a hack. "I
use the XYZ rule of bypassing and all my boards work". Yeah, but what
does that prove? Mostly it means using way more caps than needed.

I often include SMA connectors on PCB layouts, so I can TDR/TDT the power planes
on bare boards and measure the plane noise on operating boards.

A plane/pour system is a good HF cap all by itself. Adding a few more ceramic
bypasses here and there makes it better. It's pretty much that simple. Of
course, if you expect gross low-frequency current steps, you need enough bulk
capacitance to handle that until the power supply can respond.

Most systems are grossly over-bypassed. And the classic "use lots of different
value caps" papers were mostly authored by people who sell caps.

I won't argue about the "over-bypassed" boards. But if you use the
methods that are promoted by the rational engineers who *don't* sell
caps, you can actually use a lot fewer bypass caps than if you just use
one value.

I do mixed-signal stuff, uPs and FPGAs and fast ADCs and picosecond delay
generators. I don't use a lot of caps and I've never used too few.

Here's a signal conditioner and a 250 MHz 12-bit ADC inches away from a big FPGA
and a bunch of switching power supplies and line drivers. It has a few 330 nF
bypass caps here and there. It worked first time. There are no parts on the
bottom side.

https://dl.dropbox.com/u/53724080/Circuits/ESM/ESM_PCB.jpg



Absolutely!

One piece of bad info is that all systems need to be treated

Another is that high speed systems need a lot of different bypass caps. On a
multilayer board, bypassing is easy.

That's not bad info, it is useful if you actually engineer your PDS. Or
you can just scatter around a few caps and hope it works like the others
you have done seem to.

But assuming that the info on how to design the PDS for

HoJo's Black Magic book *is* silly.

I have never studied "HoJo's" book. I took a class with Lee Ritchey and
was very impressed with his knowledge, but more importantly his
techniques of understanding the theory, analyzing it in simulation, and
then proving it all correct by building the hardware. He showed that
caps on good ground/power planes don't need to be as close as possible
to the pins of the chips, again, by using all three methods.

Rick

 

[MrTallyman]

I couldn't see that it did anything useful. But thanks for trying.

The gnuplot thing works great. I double-click on a batch file, and the pdf
appears in a couple of seconds. The x-axis scaling is adaptive to the number of
points in the file, something that is apparently difficult to do in Excel.

https://dl.dropbox.com/u/53724080/Truckee/Tplot.pdf

Purty, huh?

That is not the same data set.

Send me that csv.

 

[rickman]

Me? Use more caps than needed? I use less than a tenth of the number
of caps that Xilinx recommends... average maybe three per voltage per
FPGA. Hmmm, maybe that is too many.

Using less than an FPGA maker recommends is no claim to fame. They know
nothing about your design and have to spec to the worst possible use of
their part. Given the enormously wide range possible with such devices,
especially the potential deviation from the norm, it is no wonder that
designs work with far fewer than what Xilinx recommends.

People have all sorts of beliefs about bypassing, and the beliefs are
fervently held because they work. Fact is, on a multilayer board, just
about any bypassing scheme works. I know a guy who doesn't use bypass
caps at all, and his stuff works.

I saw one big Advantest board being stuffed by a gatling gun chip
shooter. It had about 3000 bypass caps. I bet it worked too.

Yep, "all sorts of beliefs" is right, not science or engineering,
"beliefs". They may work, but they cost more too. If you want to get
to the minimum and save a few bucks on a design you have to engineer the
PDS just like you might engineer other aspects of your design, not just
toss a few caps at the power planes and hope it works.

I use 330 nF because they are cheap and we have lots of them. Why
would I mix them with any smaller value? For a given package, ESL is
independent of C, and HF impedance is dominated by ESL. More C is
better for low-frequency current steps, so use the biggest value
that's still cheap.

HF impedance is HF impedance, not inductance. Caps are self resonant
and produce a null at that frequency. They also resonate with the power
planes and produce a maximum at some frequency. So using a single value
of cap will not provide a smooth impedance curve over frequency. It
will require a lot of caps to reduce the maximum impedance to an
acceptable level, assuming you have analyzed your PDS and know what
impedance you require.

By using other sizes/values of caps you can use the nulls to minimize
the effects of the maximums and get a smoother impedance curve using
fewer caps, potentially a *lot* fewer caps.

As I said, just scatter a few 330n bypasses here and there on the
planes. I figured that out in about a half hour of TDR testing.

So all of your designs have the same requirements? What was the
impedance vs. frequency curve you got from that?

Rick

 

[[email protected]]

On Sun, 13 Jan 2013 14:38:26 -0800, John Larkin

Has anyone here done a multilayer board, with power and ground planes, where
your bypassing scheme *didn't* work?

I haven't but a cow-orker has. I fixed it with a few (8, IIRC) caps.
His next board spin had a cap everywhere there was space to put two
leads .100" apart (radial caps, before SMT).

I have had some low frequency problems, mostly slow bounces or LDO oscillations,
but they weren't high-frequency bypassing issues, more regulator loop dynamics
things.

This was a problem with dI/dt on the power planes. TTL and really
ugly spikes everywhere. The edge-triggered TTL clocks really didn't
like it at all.

That said, I'm sure I'm guilty of using far too many caps. It's a lot
easier to rationalize in a design review than "too" few. I'm doing
prototype or "platform" work now, so cost really isn't an issue,
though. A few bucks is cheap insurance. When they go to make a
million, it's a different story but it's not my design anymore.

OTOH, our prototype contract assembly house forgot a bunch on the DSPs
on the first spin of one of my boards. I only noticed it because I
got the PLL on the wrong voltage and was looking for a place to attach
a wire.

 

[Allan Herriman]

Has anyone here done a multilayer board, with power and ground planes,
where your bypassing scheme *didn't* work?

I've never had a bypassing failure when I've used planes.


I have an FPGA design I call "Chip Heater" which basically turns much of
the FPGA into a dummy load. I use it for validating my power supply
designs on my boards that have FPGAs. I can get it to periodically gate
the clock to investigate the response of the power supply to load current
steps.

The advantage of using the actual FPGA as the load (rather than a
separate power supply tester / dummy load) is that it tests the actual
component that matters. The only test equipment I need is a scope to
look at the voltages.

It's not too hard to get under 20mV total voltage variation (transient +
resitive drop + load regulation) from a fast 5A step.
It can't be done without a few chunky Al-poly caps to handle the low
frequencies though, at least not for the DC/DC converters I use.


[OT] I did have a surprise a few years ago when an FPGA design drawing
about 15A caused too much voltage drop across a part of a plane due to
the sheet resistance (about an ohm per square on an inner layer).

Adding a large fill on an outer layer in parallel with that plane fixed
the problem on a subsequent revision of the design.


Regards,
Allan

 

[[email protected]]

I've never had a bypassing failure when I've used planes.

I have an FPGA design I call "Chip Heater" which basically turns much of
the FPGA into a dummy load.  I use it for validating my power supply
designs on my boards that have FPGAs.  I can get it to periodically gate
the clock to investigate the response of the power supply to load current
steps.

We did one test design that clocked every flop on a Cyclone chip at 250 MHz,
just to satisfy our customer that we had enough power and cooling for any
conceivable expansion.

Banging the clock on and off is a good idea, to test the low-frequency response
of the power supplies.

On older Xilinx FPGAs that had internal tri-state busses, the "right" config
file could blow up a chip.

The advantage of using the actual FPGA as the load (rather than a
separate power supply tester / dummy load) is that it tests the actual
component that matters.  The only test equipment I need is a scope to
look at the voltages.

Agree. The next thing to add (which we sometimes do) is some convenient coax
connectors, SMBs or some such, to tap into the ground/power planes. It's hard to
get an honest eval of plane noise with a scope probe.

Scope probes suck, mostly.

It's not too hard to get under 20mV total voltage variation (transient +
resitive drop + load regulation) from a fast 5A step.
It can't be done without a few chunky Al-poly caps to handle the low
frequencies though, at least not for the DC/DC converters I use.

Right. Alum polymers are awesome.

[OT] I did have a surprise a few years ago when an FPGA design drawing
about 15A caused too much voltage drop across a part of a plane due to
the sheet resistance (about an ohm per square on an inner layer).

15 AMPS?!!!

I believe a modern desktop cpu calls for something like 50A of core
and 8A of IO supply at ~1V

-Lasse

 

[[email protected]]

Has anyone here done a multilayer board, with power and ground planes,
where your bypassing scheme *didn't* work?

I've never had a bypassing failure when I've used planes.

I have an FPGA design I call "Chip Heater" which basically turns much of
the FPGA into a dummy load.  I use it for validating my power supply
designs on my boards that have FPGAs.  I can get it to periodically gate
the clock to investigate the response of the power supply to load current
steps.

We did one test design that clocked every flop on a Cyclone chip at 250 MHz,
just to satisfy our customer that we had enough power and cooling for any
conceivable expansion.

Banging the clock on and off is a good idea, to test the low-frequency response
of the power supplies.

On older Xilinx FPGAs that had internal tri-state busses, the "right" config
file could blow up a chip.

The advantage of using the actual FPGA as the load (rather than a
separate power supply tester / dummy load) is that it tests the actual
component that matters.  The only test equipment I need is a scope to
look at the voltages.

Agree. The next thing to add (which we sometimes do) is some convenient coax
connectors, SMBs or some such, to tap into the ground/power planes. It's hard to
get an honest eval of plane noise with a scope probe.

Scope probes suck, mostly.

It's not too hard to get under 20mV total voltage variation (transient +
resitive drop + load regulation) from a fast 5A step.
It can't be done without a few chunky Al-poly caps to handle the low
frequencies though, at least not for the DC/DC converters I use.

Right. Alum polymers are awesome.

[OT] I did have a surprise a few years ago when an FPGA design drawing
about 15A caused too much voltage drop across a part of a plane due to
the sheet resistance (about an ohm per square on an inner layer).

15 AMPS?!!!

I believe a modern desktop cpu calls for something like 50A of core
and 8A of IO supply at ~1V

The original PPC970MP sucked down about 100A at ~1.25V. Mobile CPUs
are around 35W at about 1V, so 50A for a desktop CPU isn't outrageous.

 

[rickman]

But it always does. And I can't save a few bucks when I'm using 20 cents worth
of bypass caps on a whole board.

I never said anything about your boards. I don't know what the PDS
requirements of your boards are. Do you?

Superstition. All my boards work with very few caps.

You can ignore PDS design on your boards and if they work, they work.
But to say that engineering is "superstition" puts the bad light on you.
This is not the first time you have described a technique that just
"got the job done" without understanding what it was doing or why.
That's not really engineering. It's not always bad, but it's not
engineering. It's just pushing stuff around until it works.

TDR is time domain, so I didn't measure z-vs-f. TDR shows step response. What I
observed is that a power:ground plane pair looks like a very good, low ESL+ESR,
fairly low-Q capacitor. Or you can think of it as a very low impedance, pretty
lossy sheet transmission line. As you add bypass caps pretty much anywhere, the
impedance goes down.

When you say the PDS looks like a good low-Q capacitor, what exactly
were your requirements on the PDS? At what frequency does the impedance
go down when you add caps? Do you know the frequency content of your
power noise?

My point is you weren't doing engineering because you didn't know what
you needed from the PDS and you didn't properly characterize it to meet
requirements. You just winged it. Like I said above, that is not
engineering. It's ok until it doesn't work anymore.

Has anyone here done a multilayer board, with power and ground planes, where
your bypassing scheme *didn't* work?

What bypassing scheme is that? I'm not proposing a bypassing scheme. I
am saying that to fully engineer a PDS you need to evaluate your needs
and then design the PDS to meet those requirements. If a single value
of cap does the job, that's fine. But if your requirements are such
that you need a specific impedance over a wide frequency range then you
may need more than one value or package size cap to minimize the
impedance peaks of the interaction between your cap and the power planes.

I have had some low frequency problems, mostly slow bounces or LDO oscillations,
but they weren't high-frequency bypassing issues, more regulator loop dynamics
things.

Ok, so your PDS requirements were very easy to meet. That doesn't mean
the techniques used by others are "superstition".

Rick

 

[josephkk]

On Sun, 13 Jan 2013 14:38:26 -0800, John Larkin wrote:

Has anyone here done a multilayer board, with power and ground planes,
where your bypassing scheme *didn't* work?

I've never had a bypassing failure when I've used planes.

I have an FPGA design I call "Chip Heater" which basically turns much of
the FPGA into a dummy load.  I use it for validating my power supply
designs on my boards that have FPGAs.  I can get it to periodically gate
the clock to investigate the response of the power supply to load current
steps.

We did one test design that clocked every flop on a Cyclone chip at 250 MHz,
just to satisfy our customer that we had enough power and cooling forany
conceivable expansion.

Banging the clock on and off is a good idea, to test the low-frequency response
of the power supplies.

On older Xilinx FPGAs that had internal tri-state busses, the "right"config
file could blow up a chip.



The advantage of using the actual FPGA as the load (rather than a
separate power supply tester / dummy load) is that it tests the actual
component that matters.  The only test equipment I need is a scopeto
look at the voltages.

Agree. The next thing to add (which we sometimes do) is some convenient coax
connectors, SMBs or some such, to tap into the ground/power planes. It's hard to
get an honest eval of plane noise with a scope probe.

Scope probes suck, mostly.



It's not too hard to get under 20mV total voltage variation (transient +
resitive drop + load regulation) from a fast 5A step.
It can't be done without a few chunky Al-poly caps to handle the low
frequencies though, at least not for the DC/DC converters I use.

Right. Alum polymers are awesome.



[OT] I did have a surprise a few years ago when an FPGA design drawing
about 15A caused too much voltage drop across a part of a plane due to
the sheet resistance (about an ohm per square on an inner layer).

15 AMPS?!!!

I believe a modern desktop cpu calls for something like 50A of core
and 8A of IO supply at ~1V

The original PPC970MP sucked down about 100A at ~1.25V. Mobile CPUs
are around 35W at about 1V, so 50A for a desktop CPU isn't outrageous.

Indeed, browsing some AMD chips, peaks of near 75 A at 1.4 volts are
normal, averages are a bit lower due to package continuous dissipation
being 110 W or less. 32 nm SOI process.

?-)

 

[Chairman Meow]

On Sun, 06 Jan 2013 14:13:47 -0800, John Larkin



That is not the same data set.

Send me that csv.

22,000 data points. Yours? Averages apparently.

Lots of zeros in that data too. I replaced that with cut and pastes of
existing data for the purpose of making the plot.

I have one that handles leap years too.

Not very 'purty' at all.
Mine is, however.

http://www.mediafire.com/?oct6lczbct3wl

 

[[email protected]]

On Jan 14, 5:38 pm, John Larkin

On Sun, 13 Jan 2013 14:38:26 -0800, John Larkin wrote:

Has anyone here done a multilayer board, with power and ground planes,
where your bypassing scheme *didn't* work?

I've never had a bypassing failure when I've used planes.

I have an FPGA design I call "Chip Heater" which basically turns much of
the FPGA into a dummy load. I use it for validating my power supply
designs on my boards that have FPGAs. I can get it to periodically gate
the clock to investigate the response of the power supply to load current
steps.

We did one test design that clocked every flop on a Cyclone chip at 250 MHz,
just to satisfy our customer that we had enough power and cooling for any
conceivable expansion.

Banging the clock on and off is a good idea, to test the low-frequency response
of the power supplies.

On older Xilinx FPGAs that had internal tri-state busses, the "right" config
file could blow up a chip.



The advantage of using the actual FPGA as the load (rather than a
separate power supply tester / dummy load) is that it tests the actual
component that matters. The only test equipment I need is a scope to
look at the voltages.

Agree. The next thing to add (which we sometimes do) is some convenient coax
connectors, SMBs or some such, to tap into the ground/power planes. It's hard to
get an honest eval of plane noise with a scope probe.

Scope probes suck, mostly.



It's not too hard to get under 20mV total voltage variation (transient +
resitive drop + load regulation) from a fast 5A step.
It can't be done without a few chunky Al-poly caps to handle the low
frequencies though, at least not for the DC/DC converters I use.

Right. Alum polymers are awesome.



[OT] I did have a surprise a few years ago when an FPGA design drawing
about 15A caused too much voltage drop across a part of a plane due to
the sheet resistance (about an ohm per square on an inner layer).

15 AMPS?!!!


I believe a modern desktop cpu calls for something like 50A of core
and 8A of IO supply at ~1V

The original PPC970MP sucked down about 100A at ~1.25V. Mobile CPUs
are around 35W at about 1V, so 50A for a desktop CPU isn't outrageous.

I remember seeing the Clark boards for a late-model bipolar mainframe, a
3090ES or something like that, circa 1990. One of the power supply
busses was +3.3V at 9000 amps. It was a heavy solid copper angle, about
2 inch by 2 inch by 1/4 inch.

ISTR, mainframes used either +1.25V and -3.0V (ECL, or "CSEF") or
ground, -1.5, and -3V (TTL). There weren't many TTL models (only one
of the 3080s, IIRC). 9kA seems high but not tremendously so (the CPU
was 9 TCMs at 1.5KW).

 

[[email protected]]

On 1/14/2013 5:40 PM, [email protected] wrote:
On Mon, 14 Jan 2013 12:36:05 -0800 (PST), "[email protected]"

On Jan 14, 5:38 pm, John Larkin

On Sun, 13 Jan 2013 14:38:26 -0800, John Larkin wrote:

Has anyone here done a multilayer board, with power and ground planes,
where your bypassing scheme *didn't* work?

I've never had a bypassing failure when I've used planes.

I have an FPGA design I call "Chip Heater" which basically turns much of
the FPGA into a dummy load. I use it for validating my power supply
designs on my boards that have FPGAs. I can get it to periodically gate
the clock to investigate the response of the power supply to load current
steps.

We did one test design that clocked every flop on a Cyclone chip at 250 MHz,
just to satisfy our customer that we had enough power and cooling for any
conceivable expansion.

Banging the clock on and off is a good idea, to test the low-frequency response
of the power supplies.

On older Xilinx FPGAs that had internal tri-state busses, the "right" config
file could blow up a chip.



The advantage of using the actual FPGA as the load (rather than a
separate power supply tester / dummy load) is that it tests the actual
component that matters. The only test equipment I need is a scope to
look at the voltages.

Agree. The next thing to add (which we sometimes do) is some convenient coax
connectors, SMBs or some such, to tap into the ground/power planes. It's hard to
get an honest eval of plane noise with a scope probe.

Scope probes suck, mostly.



It's not too hard to get under 20mV total voltage variation (transient +
resitive drop + load regulation) from a fast 5A step.
It can't be done without a few chunky Al-poly caps to handle the low
frequencies though, at least not for the DC/DC converters I use.

Right. Alum polymers are awesome.



[OT] I did have a surprise a few years ago when an FPGA design drawing
about 15A caused too much voltage drop across a part of a plane due to
the sheet resistance (about an ohm per square on an inner layer).

15 AMPS?!!!


I believe a modern desktop cpu calls for something like 50A of core
and 8A of IO supply at ~1V

The original PPC970MP sucked down about 100A at ~1.25V. Mobile CPUs
are around 35W at about 1V, so 50A for a desktop CPU isn't outrageous.


I remember seeing the Clark boards for a late-model bipolar mainframe, a
3090ES or something like that, circa 1990. One of the power supply
busses was +3.3V at 9000 amps. It was a heavy solid copper angle, about
2 inch by 2 inch by 1/4 inch.

ISTR, mainframes used either +1.25V and -3.0V (ECL, or "CSEF") or
ground, -1.5, and -3V (TTL). There weren't many TTL models (only one
of the 3080s, IIRC). 9kA seems high but not tremendously so (the CPU
was 9 TCMs at 1.5KW).

Could have been -3V. I remember it was about 27 kW, which would be
about right.

Do you remember the system or approximate year? Just trying to
refresh my memory, too.

 

[Chairman Meow]

22,000 data points. Yours? Averages apparently.

Lots of zeros in that data too. I replaced that with cut and pastes of
existing data for the purpose of making the plot.

I have one that handles leap years too.

Not very 'purty' at all.
Mine is, however.

http://www.mediafire.com/?oct6lczbct3wl

The spaces both before and after your date field entries is LAME
formatting.

It requires additional handling after the import operation.

Pretty lame. Making a proper CSV file is about as academic as hooking
up a printer cable.

Either your data logger or *your* programming of your data logger
output is adding these spaces, and they are NOT needed. a CSV will fill
field values and you do not need to space anything off for it.

 

[rickman]

ISTR, mainframes used either +1.25V and -3.0V (ECL, or "CSEF") or
ground, -1.5, and -3V (TTL). There weren't many TTL models (only one
of the 3080s, IIRC). 9kA seems high but not tremendously so (the CPU
was 9 TCMs at 1.5KW).

Geeze! 9000 Amps!!! That's a hell of a machine. I thought I worked on
a city dimmer, powered by 220V and internally running big braided cables
for DC power distribution. Lots of ECL gate arrays. But I guess that
is still in the minor leagues compared to this.

It was a fast machine though. Around 1985 and it did 100 MFLOPS. I
think it was the fastest machine at the time other than a Cray, which of
course, it didn't really come close to, but it was well under a mil. I
think the base price was about $200k. These days a cell phone does that
in fixed point.

Rick

 

[Chairman Meow]

Excel is lame.

No... John... YOU are lame.

You are, in fact, as lame as a person claiming to be a man can get.
This "excel is lame' crack proves that fact.

Gnuplot is smart enough to parse it.

excel can also parse it.

The problem is your retarded decision to add the space to begin with.

The only element in the whole thing NOT smart enough is you.

 

[rickman]

Sure. We typically have anywhere from 4 to 12 power rails. Like +0.9, +1.2,
+2.5, +3.3, +5, +5A, -5A, +12, and a couple of VREF type things. Sometimes more,
like +-48 or whatever, or +1.1 for some PHY type thing.

This isn't going anywhere. It is clear that you don't really understand
PDS design and have done lots of stuff where you can get away with
typical designs.

Right. Why pay for courses and do a lot of engineering when power supplies are
easy and almost always work?

I'm not talking about power supplies. I'm talking about the PDS, power
distribution system. "almost"? That's what I'm talking about.

The mixing of caps with various SRFs is mostly done based on authority and
hearsay. Sure it works. And it works just as well if you don't do it.

I've already quoted Lee Ritchey. I took his course where he shows the
theory, simulation results and then the board that he built to test it.
That's not "hearsay".

Maybe you're talking about science. Engineering is doing what works efficiently.
I don't do extensive analysis - thermal, magnetic, mechanical, nuclear - when I
don't need to.

Yes, your designs have not needed significant engineering in the PDS.
That's not true for all designs and may not be true for yours in the
future.

It's not always bad, but it's not

That's what engineering is. You don't do full Maxwells Equations and
first-principles quantum physics when you design a simple opamp circuit. Neither
do I. But we don't "push stuff around." We draw schematics, lay out boards, and
have people assemble them for us. No prototypes, not much simulation. Over 95%
of the time, it works on the first try.

You can diss the idea all you want, but it is important to know how to
apply proper engineering when it is needed. I don't consider 95% to be
very good really. Startup companies have folded because of design
failures like this.

Normal stuff, mixed-signal systems, uPs and FPGAs and ADCs and opamps and
things. Lots of picosecond timing and low-level signal conditioning. I've posted
lots of pics of my PC boards.

That's not a PDS requirement. In other words, you haven't built
anything that needed rigorous analysis of the PDS.

At what frequency does the impedance

I work in time domain, not frequency. I TDR a plane and see its current-step
response. It looks like, say, a 1500 pF cap without much personality, just some
very fuzzy hints of edge/corner reflections. Add some bypass caps, and it looks
like a bigger cap, and the reflection hints go away. It's not a big deal.

I didn't ask about the PDS, I asked about the noise the chips produce.

So far, everything works. Engineering hours are better spent on things that add
value.

You keep saying things like 95%, "almost" and "so far". That's not
engineering.

If they use 400 caps, when 20 would do, that's not good engineering.

Now you are talking nonsense. Your method of adding single value caps
until you can get the board to work is the one that uses lots more caps
to get the same board impedance across the spectrum.

The only bypassing problems that I sometimes see are low frequency stuff,
microseconds to milliseconds. That deserves attention. When you see a lot of
jitter in a fast circuit, look first for *low* frequency power supply noise.

Ok, if you can get your boards to work this way, that's fine. I agree
that most designs don't need so much attention to the PDS. I'm just
saying that the idea that some designs need to be done well and properly
is not "superstition". Let me know when you design something
transmitting or receiving 10+ Gbps without giving the *full* design a
proper noise analysis.

Rick

 

[josephkk]

CPUs are special in that they can go from low current to scores of amps in
nanoseconds, as some process wakes up. FPGA designs seldom do that... they
mostly just tick along, clocking all of their flops all the time.

In both cases it is a combination of design and workload dependencies.
Just the same most FPGA designs are a lot less sensitive to workload.

?-)

 

[josephkk]

Almost 28K lines so far. Spot temperature measurements, not averages.

I had to extend the plot y-axis to -10F. We had a cold front move though. The
official low temp in Truckee, at the airport in Martis Valley, was -22F,but
that station is out in the open, always higher/lower than realistic temps in the
woods.

https://dl.dropbox.com/u/53724080/Truckee/Tplot.pdf



I don't see any zeroes.



I am *not* going to execute a spreadsheet posted by some Chairman Meow who has
threatened me numerous times and who won't reveal his actual name.

The gnuplot thing works great.

Should anybody give a flying donut at a rolling leap, mediafire has a
preview feature that will give a look at what the result might look like
without the file ever being transferred to your computer. I used it and
joke sheppard's file ain't nearly as 'purty' as your plots. Three
separate graphs, can't 'e get XL to do multiple lines on one chart? And
far less timespan, just junk by comparison.

?-)

 

[[email protected]]

In both cases it is a combination of design and workload dependencies.
Just the same most FPGA designs are a lot less sensitive to workload.

As John mentioned, all flops in an FPGA get clocked simultaneously.
Even clock gating doesn't drop much power because the entire clock
tree is still hot. FPGAs don't use much in the way of dynamic power
management, or really, power management of any kind. These are all
"tricks" that CPUs have used for decades that really aren't applicable
to FPGAs.

 

[CellShocked]

Excel is for people who never learned to program.

That is about as stupid a remark as I have seen you make in a long
time.

It also proves that you have barely even a cursory grasp of
spreadsheets in general, including ALL versions of excel.

Especially the more recent releases.

You could not be farther from iterating facts if you were actually
trying to.