Sawtooth-shaped oscillation from op-amp buffer?

[BW]

Hi!

I have a very simple op-amp circuit built around the MAX4475 single op-
amp. It is a non-inverting amplifier with gain 2x (using a resistor-
divider 5k6 + 5k6), and dumping to a 1 uF cap on the output. On the
(positive) input is a single DC voltage from a bandgap-based D/A-
converter.

Now, the strangest thing: when measuring on the op-amp output, I get a
near perfect sawtooth-shaped oscillation of perhaps 10-20 mV,
frequency maybe 30 kHz (which is not visible on the input). Varying
the resistors and/or output cap, shifts the oscillation in size and
frequency.

I'm no op-amp guru, does this sound like a pole in the transfer-
function ? Shouldn't that give a nice sine-wave ? Why the perfect saw-
tooth? Adding a forward compensation capacitor of 12 pF (as per the
datasheet suggestion exactly) doesn't change anything at all.

Basically I'm asking if anyone know if this failure-mode is a typical
decompensated op-amp buffer or if it sounds strange and could signify
some major magic ?

Initially I had the op-amp configured to drive the gate of an external
FET, with the same results strangely enough.

Removing the output 1 uF cap increases the oscillation. Changing the
output cap to 47 uF reduces the oscillation. I hesitate to do this
permanently - I want to understand why it oscillates in that way in
the first place...

Next test is to replace the op-amp with some other brand and see if
the same problem persists, of course.

Best regards,
Bjorn

 

[Spehro Pefhany]

Hi!

I have a very simple op-amp circuit built around the MAX4475 single op-
amp. It is a non-inverting amplifier with gain 2x (using a resistor-
divider 5k6 + 5k6), and dumping to a 1 uF cap on the output. On the
(positive) input is a single DC voltage from a bandgap-based D/A-
converter.

Now, the strangest thing: when measuring on the op-amp output, I get a
near perfect sawtooth-shaped oscillation of perhaps 10-20 mV,
frequency maybe 30 kHz (which is not visible on the input). Varying
the resistors and/or output cap, shifts the oscillation in size and
frequency.

I'm no op-amp guru, does this sound like a pole in the transfer-
function ? Shouldn't that give a nice sine-wave ? Why the perfect saw-
tooth? Adding a forward compensation capacitor of 12 pF (as per the
datasheet suggestion exactly) doesn't change anything at all.

Basically I'm asking if anyone know if this failure-mode is a typical
decompensated op-amp buffer or if it sounds strange and could signify
some major magic ?

Initially I had the op-amp configured to drive the gate of an external
FET, with the same results strangely enough.

Removing the output 1 uF cap increases the oscillation. Changing the
output cap to 47 uF reduces the oscillation. I hesitate to do this
permanently - I want to understand why it oscillates in that way in
the first place...

Next test is to replace the op-amp with some other brand and see if
the same problem persists, of course.

Best regards,
Bjorn

Well, the data sheet says you shouldn't load the output with more than
200pF. 200pF << 1uF. Also a MOSFET gate is likely >> 200pF.

 

[[email protected]]

The output resistance of the amp times the capacitive load puts an RC
lowpass pole into the feedback loop.  That's often enough to make even
unity-gain stable amps oscillate.  The usual trick is to put a resistor
in series with the load.  If you need better DC accuracy than that will
give you, you can take the DC feedback from the load capacitor and the
AC feedback from the op amp output.

Cheers,

Phil Hobbs

Ah yes, a trick from the National analog book.

 

[BW]

...
The output resistance of the amp times the capacitive load puts an RC
lowpass pole into the feedback loop.  That's often enough to make even
unity-gain stable amps oscillate.  The usual trick is to put a resistor
in series with the load.  If you need better DC accuracy than that will
give you, you can take the DC feedback from the load capacitor and the
AC feedback from the op amp output.

The strange thing is that my circuit (when it included the FET-buffer)
is a verbatim copy of this article written by Ken Yang of Maxim in
EDN:

http://www.edn.com/article/CA608157.html

title is "Ultra-low-noise low-dropout regulator achieves 6-nv/sqrt(hz)
noise floor". In this he explicitely breaks the <200 pF output loading
of the MAX4475 (their own chip!) when it is driving the gate of the
FDN302P (882 pF). Maybe it was stable when he tested it ?

In any case, I tried with series resistance between the op-amp output
and the FET-gate, first with 47 ohm then with 1 kohm. The sawtooth
wave persisted and actually increased in amplitude when the resistance
increased..

Very strange (strangest part is that a guy from Maxim designs an app-
note for their own op-amps which might be inherently unstable).
Perhaps I should mail him and ask...

/Bjorn

 

[Tim Williams]

Ok then...

Supply bypass?

Tim

--
Deep Friar: a very philosophical monk.
Website: http://webpages.charter.net/dawill/tmoranwms

In any case, I tried with series resistance between the op-amp output
and the FET-gate, first with 47 ohm then with 1 kohm. The sawtooth
wave persisted and actually increased in amplitude when the resistance
increased..

Very strange (strangest part is that a guy from Maxim designs an app-
note for their own op-amps which might be inherently unstable).
Perhaps I should mail him and ask...

/Bjorn

 

[Spehro Pefhany]

The strange thing is that my circuit (when it included the FET-buffer)
is a verbatim copy of this article written by Ken Yang of Maxim in
EDN:

http://www.edn.com/article/CA608157.html

title is "Ultra-low-noise low-dropout regulator achieves 6-nv/sqrt(hz)
noise floor". In this he explicitely breaks the <200 pF output loading
of the MAX4475 (their own chip!) when it is driving the gate of the
FDN302P (882 pF). Maybe it was stable when he tested it ?

In any case, I tried with series resistance between the op-amp output
and the FET-gate, first with 47 ohm then with 1 kohm. The sawtooth
wave persisted and actually increased in amplitude when the resistance
increased..

Very strange (strangest part is that a guy from Maxim designs an app-
note for their own op-amps which might be inherently unstable).
Perhaps I should mail him and ask...

It's not strange, it's *typical*. Don't blindly trust application note
circuits, *ever*! I get the impression they are done by junior
engineers, fiddling around in the lab to make interesting circuits,
and not always checked all that well. You are not the first one to be
burned!

 

[Eeyore]

Hi!

I have a very simple op-amp circuit built around the MAX4475 single op-
amp. It is a non-inverting amplifier with gain 2x (using a resistor-
divider 5k6 + 5k6), and dumping to a 1 uF cap on the output. On the
(positive) input is a single DC voltage from a bandgap-based D/A-
converter.

What do you mean by "dumping to a 1 uF cap on the output" ? What's its
purpose if any other than to make the circuit unstable ?

Graham

 

[Eeyore]

The strange thing is that my circuit (when it included the FET-buffer)
is a verbatim copy of this article written by Ken Yang of Maxim in
EDN:

http://www.edn.com/article/CA608157.html

title is "Ultra-low-noise low-dropout regulator achieves 6-nv/sqrt(hz)
noise floor". In this he explicitely breaks the <200 pF output loading
of the MAX4475 (their own chip!) when it is driving the gate of the
FDN302P (882 pF). Maybe it was stable when he tested it ?

Since the fet is acting as a voltage follower, the op-amp won't see the full
Cgs / Ciss.

Graham

 

[John Devereux]

Hi!

I have a very simple op-amp circuit built around the MAX4475 single op-
amp. It is a non-inverting amplifier with gain 2x (using a resistor-
divider 5k6 + 5k6), and dumping to a 1 uF cap on the output. On the
(positive) input is a single DC voltage from a bandgap-based D/A-
converter.

Are you sure you have the opamp inputs the right way around? The
circuit you posted a link to had the *negative* input driven from the
reference. (The external P-Fet inverts the feedback, so you need to
use the opamp inputs the opposite way around than usual).

Failing that, did you try Phil Hobbs advice about AC feedback from the
opamp output and DC from the P-Fet output?

[...]

 

[[email protected]]

Yup--Widlar's AN4, from 1968--still good reading after 40 years.  It's
Figure 15--seehttp://www.national.com/an/AN/AN-4.pdf.

Cheers,

Phil Hobbs

Damn those guys were good. There is also that trick with the high
speed buffer in the "can" where you solder the output to the can to
reduce input capacitance. They were both smart and practical.

National never gave the analog guys much respect, hence the creation
of Linear Technology. It is no coincidence that their engineering
building has a sign outside that says "Home of the Gurus". Though I
worked for the competition at the time, I had and still have great
respect for their designers.

 

[James Arthur]

The strange thing is that my circuit (when it included the FET-buffer)
is a verbatim copy of this article written by Ken Yang of Maxim in
EDN:

http://www.edn.com/article/CA608157.html

title is "Ultra-low-noise low-dropout regulator achieves 6-nv/sqrt(hz)
noise floor". In this he explicitely breaks the <200 pF output loading
of the MAX4475 (their own chip!) when it is driving the gate of the
FDN302P (882 pF). Maybe it was stable when he tested it ?

In any case, I tried with series resistance between the op-amp output
and the FET-gate, first with 47 ohm then with 1 kohm. The sawtooth
wave persisted and actually increased in amplitude when the resistance
increased..

This is how it's done:

|
|\ ||-+
--------|+\ ___ ||-> Q1
| >---o---|___|-----||-+
.----|-/ | |
| |/ | R1 o------>
| | |
| C1 --- |
| --- .-.
| | | | R2
| | | |
| | '-'
| | |
'-----------o----------------o
|
.-.
| | R3
| |
'-'
|
|
===
GND
(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

R1 keeps the FET from loading from the op-amp, and C1
eliminates (destabilizing) R1 * Cgs(Q1) feedback delay.

Cheers,
James Arthur

 

[James Arthur]

The FET in the OP's circuit is running common source, with feedback
going to the + input of the op amp. Because the FET is an inverting
stage, the split feedback trick doesn't work in this simple form.

Cheers,

Phil Hobbs

Oops, I biffed the ASCII drawing. Thanks for the catch.
Corrected, above.

It doesn't have the low-dropout, but should still let
the op amp cancel Q1's noise.

Cheers,
James Arthur

 

[James Arthur]

The source follower bootstraps the Cgs anyway, so it shouldn't need the
split feedback as badly. It also doesn't have the low-dropout
feature--one might as well use an LM317. Something like an emitter
follower driving the FET would be the ticket.

Cheers,

Phil Hobbs

Or, to keep the low drop-out, why not:
V+
-+-
|| Ca |
.---||---. |
| || | ||--+
| | | |
___ | |\ | ||->' Q1
...----o----|___|---o--|-\ | ___ |
| Ra | >--o-|___|--||--.
C1 --- .--|+/ Rb |
100uF--- | |/ o----->
| | |
=== | .-.
GND | | | R2
| | | 3.9k
| '-'
| |
'---------------------o
|
.-.
| | R3
| | 2.4k
'-'
|
===
GND

(created by AACircuit v1.28.4 beta 13/12/04 www.tech-chat.de)

The (+) input already sees R3 || R2 = 1.5k, so a smallish Ra
shouldn't wreck the noise performance.

Cheers,
James Arthur

 

[Mark]

That might work fine, depending on the gain of the FET/output
bypass/load resistance system.  The (Z0+Rb)Cgs pole is still inside the
outer loop, and the noninverting gain doesn't drop below 1.0 even with
the integrator.  That can be fixed by adding enough output bypass
capacitance that the outer feedback loop is stable regardless of load.
Getting the transient response to be decent will be a bit of a problem,
but then I think pretty much all LDOs have that difficulty.

Cheers,

Phil Hobbs- Hide quoted text -

- Show quoted text -

to BW,
this is a long shot but try it just in case

try adding a 10K ohm resistor from the op amp output to V-- or to V +
+.

sometimes these fancy output stages can set up a deadband oscillation
if they are loaded with an AC load but no DC load..

Mark

 

[BW]

to BW,
this is a long shot but try it just in case

try  adding a  10K ohm resistor from the op amp output to V-- or to V+
+.

sometimes these fancy output stages can set up a deadband oscillation
if they are loaded with an AC load but no DC load..

Thanks.

Just to give some feedback to the thread after some more experiments:
the FET in question at the beginning, from the Maxim app-note, had a
gate-capacitance of 882 pF, well beyond the rated maximum stable load
of the op-amp of 200 pF. Various schemes were proposed to deal with
that. Well I bought some FET's with 1/10th of the gate capacitance and
I increased the output capacitor by a factor of 10 and this removed
the
oscillations on most driving points (although it seemed to appear in
some
still). I haven't tried the extra AC-feedback. This works well enough
for
me to continue the rest of the design meanwhile at least.

Seems like the phenomenon is a standard control-theoretic problem
and should be treated as such, of course. I'm a theoretical guy so I
would want to be able to spice-simulate this, but I couldn't get the
oscillation to appear in the spice model.. oh well. Perhaps it is
dependent on some noise being present to trigger the resonance in
the feedback loop.

The reason the oscillation is sawtooth-shaped isn't it probably
because the op-amps output-stage is asymmetric with regards to
sinking and sourcing current to the FET-gate? It desperately tries to
correct the input difference, and it has to charge the gate, the
conductance changes, it has to discharge the gate etc. all this
happening at different rates => sawtooth.

I went and ordered a book dedicated only to voltage and current-
sources, which will be interesting to read

/Bjorn