Maker Pro
Maker Pro

PSpice convergence prob

A

Active8

Jan 1, 1970
0
hi:

here's the message:

ERROR -- Convergence problem in transient analysis at Time = 3.052E-15
Time step = 3.052E-15, minimum allowable step size = 20.00E-
15

These voltages failed to converge:

V(M_UN0014) = -20.00V \ 20.00V

These supply currents failed to converge:

I(X_U1.Edemout) = 20.00uA \ -20.00uA

These devices failed to converge:
X_U1.Edemout

ERROR -- Discontinuing simulation due to convergence problem

node 0014 is the ground, i think. i don't know about Edemout. i don't
know what time step has to do with it.

TIA,
mike
 
J

Jim Thompson

Jan 1, 1970
0
hi:

here's the message:

ERROR -- Convergence problem in transient analysis at Time = 3.052E-15
Time step = 3.052E-15, minimum allowable step size = 20.00E-
15

These voltages failed to converge:

V(M_UN0014) = -20.00V \ 20.00V

These supply currents failed to converge:

I(X_U1.Edemout) = 20.00uA \ -20.00uA

These devices failed to converge:
X_U1.Edemout

ERROR -- Discontinuing simulation due to convergence problem

node 0014 is the ground, i think. i don't know about Edemout. i don't
know what time step has to do with it.

TIA,
mike

"Ground" should be node "0" (zero).

"Edemout" is a node name.

...Jim Thompson
 
A

Active8

Jan 1, 1970
0
Jim-T@golana- said:
"Ground" should be node "0" (zero).

it is.
"Edemout" is a node name.

i figured that, it's part of a chip subcircuit. CD4046.

Edemout demout 0 table={ 200Meg*v(vcoin,demout)*v(off) } (-20,-20) (20,20)

ERROR -- Convergence problem in transient analysis at Time = 3.052E-15
Time step = 3.052E-15, minimum allowable step size = 20.00E-
15

These voltages failed to converge:

V(N32899) = -20.00V \ 20.00V

that node is the demod out, pin 10. it's grounded through a R.

mike
 
A

Active8

Jan 1, 1970
0
can't remember what got me thinking this - quick look at the netlist
with slow think on the brain. the grounds are named "0" and therefore
the ground net/node is "0". anyway, this error is gone now. it's still a
time step error. see other post.

mike
 
J

Jim Thompson

Jan 1, 1970
0
can't remember what got me thinking this - quick look at the netlist
with slow think on the brain. the grounds are named "0" and therefore
the ground net/node is "0". anyway, this error is gone now. it's still a
time step error. see other post.

mike

Post your netlist and settings.

...Jim Thompson
 
A

Active8

Jan 1, 1970
0
Post your netlist and settings.

sorry. next time, i'll do that from the start.
...Jim Thompson
fixed. can't reproduce the original error, which changed b4 i fixed the
circuit.

the error changed to:

ERROR -- Convergence problem in transient analysis at Time = 1.112E-03
Time step = 6.339E-15, minimum allowable step size = 20.00E-
15

These devices failed to converge:
X_U1.Evcoout X$X_U1.vcosqr_AtoD1.X1.G_Clamp

that's the vco out of a 4046 PLL. when i saw the original timestep
error, i set the rise/fall times of the reference clock way too big, i
suppose. the edge-triggered phase detector must have been feeding crap
to the filter and VCO. i suppose the demod wasn't happy either.

i don't understand the timestep error, but i guess an output convergence
error, with no obvious probs conencted to that output, means i should
look at all possible inputs that might cause the output to be wrong, eh?
just like i'd do with a real circuit and a scope. too bad i can't probe
an aborted sim.

thanks,
mike
 
J

Jim Thompson

Jan 1, 1970
0
sorry. next time, i'll do that from the start.
fixed. can't reproduce the original error, which changed b4 i fixed the
circuit.

the error changed to:

ERROR -- Convergence problem in transient analysis at Time = 1.112E-03
Time step = 6.339E-15, minimum allowable step size = 20.00E-
15

These devices failed to converge:
X_U1.Evcoout X$X_U1.vcosqr_AtoD1.X1.G_Clamp

that's the vco out of a 4046 PLL. when i saw the original timestep
error, i set the rise/fall times of the reference clock way too big, i
suppose. the edge-triggered phase detector must have been feeding crap
to the filter and VCO. i suppose the demod wasn't happy either.

i don't understand the timestep error, but i guess an output convergence
error, with no obvious probs conencted to that output, means i should
look at all possible inputs that might cause the output to be wrong, eh?
just like i'd do with a real circuit and a scope. too bad i can't probe
an aborted sim.

thanks,
mike

Probe should display up to the point of failure unless you have output
suppressed until a later time.

Could you post your schematic and netlist?

...Jim Thompson
 
A

Active8

Jan 1, 1970
0
it's below.
Probe should display up to the point of failure unless you have output
suppressed until a later time.

i may have done that. i'll remember that for future ref.
Could you post your schematic and netlist?

...Jim Thompson

ok. the schematic is just fig. 9.74 AoE 2nd ed. p. 649. it's on the
binaries group, now. subject line "4046 PLL"

in case it's hard to read, V1 is Pulse(0 5 0 1n 1n 8.33m 16.67m). i just
put those rise/fall times in to get it working. as i said, i'd set them
way to high when the timestep error came up. how high? oh, IIRC i just
popped in 25us, not thinking. it "looked" like a 60Hz sq wave, but i
don't think a 25us rise time is what the detector wanted :)

* source 4046PLL
X_U2A N28704 N34796 $G_DPWR $G_DGND 74HC04 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R5 0 N27872 330k
C_C2 N27872 N27842 1u
C_C1 N27635 N27576 680p
R_R6 N34796 0 10k
X_U3 0 N28704 M_UN0001 M_UN0002 M_UN0003 M_UN0004 M_UN0005
M_UN0006
+ M_UN0007 M_UN0008 M_UN0009 N28562 M_UN0010 M_UN0011 $G_DPWR $G_DGND
74HC4040
+ PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R1 N32899 0 100k
V_V1 N25846 0 Pulse(0 5 0 1n 1n 8.33m 16.67m)
R_R3 0 N27290 10k
X_U1 N25846 N27783 M_UN0012 M_UN0013 N28562 N27842 N27290 N27356
N27576
+ N27635 N28704 N32899 0 M_UN0014 VCC 0 $G_DPWR $G_DGND CD4046 PARAMS:
+ MNTYMXDLY=0 IO_LEVEL=0 Rin=0.3Meg S1=1 S2=0.5 M1=0.5 M2=1.0 Vx=10 Kb=
1
+ Vfree=0.0 Kc=-0.1 Vt=1.2 Vxqr=10
R_R4 0 N27356 200k
V_V2 VCC 0 9Vdc
R_R2 N27842 N27783 4.3Meg

thanks,
mike
 
Top