Power Clamp Diodes

[Jon Slaughter]

On Page 2 of

http://www.actel.com/documents/Ibis_AN.pdf

What do the power and ground clamp diodes do? How do they prevent a short if
both fets are activated at the same time?

It seems that the diodes only conduct if the ground and Vcc on the fets are
signficantly off bring the line just a diode drop below Vcc or above ground?
(if thats true then what limits the current?)

Thanks,
Jon

 

[John Larkin]

On Page 2 of

http://www.actel.com/documents/Ibis_AN.pdf

What do the power and ground clamp diodes do?

ESD protection, mostly. They can protect gate oxide from damage caused
by over-driving inputs.

How do they prevent a short if
both fets are activated at the same time?

They don't. But the logic shouldn't allow that.

It seems that the diodes only conduct if the ground and Vcc on the fets are
signficantly off bring the line just a diode drop below Vcc or above ground?
(if thats true then what limits the current?)

Nothing. If an external drive pushes enough current into an esd diode,
it dies.

Sometimes, driving an esd diode hard enough will activate a parasitic
scr from vcc to ground. That's bad, too.

John

 

[Jon Slaughter]

ESD protection, mostly. They can protect gate oxide from damage caused
by over-driving inputs.

Ok, I think I see that now. If there is a high voltage on the output then
both diodes will conduct?

They don't. But the logic shouldn't allow that.

Yeah, but is it ever possible? Surely theres a small probability that it
could happen on a transition? and if it did wouldn't a large current flow?
Or is the logic designed exactly to avoid this? or would it be for such a
short time that it would be insignificant?

Nothing. If an external drive pushes enough current into an esd diode,
it dies.

Sometimes, driving an esd diode hard enough will activate a parasitic
scr from vcc to ground. That's bad, too.

Thanks,
Jon

 

[John Larkin]

Ok, I think I see that now. If there is a high voltage on the output then
both diodes will conduct?

Only one can conduct at a time. If the externally applied voltage is
positive, the upper diode dumps the current into Vcc. If negative, the
lower diode conducts to ground. All that assumes the fets are off.

Yeah, but is it ever possible? Surely theres a small probability that it
could happen on a transition? and if it did wouldn't a large current flow?
Or is the logic designed exactly to avoid this? or would it be for such a
short time that it would be insignificant?

CMOS structures generally do have a shoot-through current, a current
spike during a transition, when both fets are partially on. It doesn't
last long and does no great harm, but it does increase power
dissipation, Vcc noise, and ground bounce.

John

 

[Jon Slaughter]

Only one can conduct at a time. If the externally applied voltage is
positive, the upper diode dumps the current into Vcc. If negative, the
lower diode conducts to ground. All that assumes the fets are off.

oh yeah... got the direction wrong on one of the diodes(memory isn't what it
used to be).

CMOS structures generally do have a shoot-through current, a current
spike during a transition, when both fets are partially on. It doesn't
last long and does no great harm, but it does increase power
dissipation, Vcc noise, and ground bounce.

ok.

Thanks,
Jon