Multiple oscillators on one chip?

[Paul Burridge]

Hi,

I think I guess what the response to this question will be but let's
see anyway...
Suppose | can source a chip from some manufacturer that has say six
unbuffered inverters within it. Can I use all six as the gain elements
for six seperate oscillators all operating at different frequencies or
is that inviting disaster?
Likewise, suppose I come across a suitable *buffered* hex inverter for
use as buffers for the multiple osciallators. Is there a problem with
that?

Thanks,

p.

 

[John Larkin]

Hi,

I think I guess what the response to this question will be but let's
see anyway...
Suppose | can source a chip from some manufacturer that has say six
unbuffered inverters within it. Can I use all six as the gain elements
for six seperate oscillators all operating at different frequencies or
is that inviting disaster?
Likewise, suppose I come across a suitable *buffered* hex inverter for
use as buffers for the multiple osciallators. Is there a problem with
that?

Thanks,

p.

Oscillators love to synchronize to each other, even crystal
oscillators of different frequencies on different circuit boards. I'm
fighting that problem right now. I have a 12.8 MHz OCXO locking to a
40 MHz rubidium-based osc on separate boards, and the locking is
messing up my statistics. 12.8 turned out to be a bad choice.

Given two nearby oscillators of frequencies f1 and f2, they will tend
to lock if n*f1 is close to m*f2 for any small values of n and m. So
you might wind up with 13 cycles of f1 aligning with 7 cycles of f2,
or any combination like that. Two or more oscillators can also
lock/unlock intermittently, or jump n:m ratios at random. The math is
messy... you have to use classic number theory (gcd's, lcm's, relative
primes) modified for near-miss cases. In my case, 12.8 * 25 = 40 * 8 =
320 MHz exactly. Even when they don't lock hard, they briefly "stick"
as the edges walk across each other, and it messes up my jitter math.

If you don't mind this sort of locking, you can certainly use all six
sections as separate oscillators.

John

 

[Stefan Heinzmann]

Hi,

I think I guess what the response to this question will be but let's
see anyway...
Suppose | can source a chip from some manufacturer that has say six
unbuffered inverters within it. Can I use all six as the gain elements
for six seperate oscillators all operating at different frequencies or
is that inviting disaster?
Likewise, suppose I come across a suitable *buffered* hex inverter for
use as buffers for the multiple osciallators. Is there a problem with
that?

No to both questions, except if you need spectrally pure oscillators, in
which case you wouldn't use unbuffered inverters anyway. Proper
bypassing is assumed, of course.

You don't need to suppose that much. Hex inverters are very commonplace,
both buffered and unbuffered.

 

[Tom Del Rosso]

In John Larkin typed:

Given two nearby oscillators of frequencies f1 and f2, they will tend
to lock if n*f1 is close to m*f2 for any small values of n and m. So
you might wind up with 13 cycles of f1 aligning with 7 cycles of f2,

I don't know any better, so how useless is this idea? Divide f1 by 13
and feed that output back to the f1 osc so it syncs to that, and do the
same for f2 divided by 7. If those signals swamped the crosstalk, could
it be done without destabilizing each oscillator just as badly as it is
now? Maybe it would introduce jitter for only a short while but then
they would stabilize?

 

[Mike]

In John Larkin typed:

I don't know any better, so how useless is this idea? Divide f1 by 13
and feed that output back to the f1 osc so it syncs to that, and do the
same for f2 divided by 7. If those signals swamped the crosstalk, could
it be done without destabilizing each oscillator just as badly as it is
now? Maybe it would introduce jitter for only a short while but then
they would stabilize?

What you're introducing is a synchronous disturbance. At best, it will have
no effect; at worst, it will introduce a large error every p cycles (p
being 13 or 7, n and m having been taken by John). Since you're talking
about deliberately feeding the divider output back into the oscillator, I
think the effect will be closer to the worst than the best. This effect is
often visible when divided clocks are used in a system.

Adding the dividers would have no effect on the original problem. If you
plot the two clocks in John's problem, you'll find that their edges slide
past each other, with their phases lining up every 625ns or so (312.5ns if
you count positive edges lining up with negative edges). When the clock
edges are closely aligned, a small amount of energy from one oscillator can
couple into the other oscillator, pulling its phase away from ideal. The
most common solutions are choosing frequencies that interfere less often,
and better isolation between the clocks.

-- Mike --

 

[Fred Bloggs]

In my case, 12.8 * 25 = 40 * 8 =
320 MHz exactly. Even when they don't lock hard, they briefly "stick"
as the edges walk across each other, and it messes up my jitter math.

Clear case of not enough reverse isolation on those output
buffers-install output isolators and notch the interfering frequency
down 100dB-use semirigid.

 

[budgie]

Clear case of not enough reverse isolation on those output
buffers-install output isolators and notch the interfering frequency
down 100dB-use semirigid.

Might be a tad more compact to *avoid* the problem by using more chips in the
starting lineup than *fixing* the problem.