Math question for a counting circuit

[kong]

I'm using the 4536 timer IC

the freq is calculated by: 1/ 2.3Rt*Ct

my component values are R1: 1k C1: 1uf



f in hz
R in ohms
C in Farads

I keep messing up somehow...I get a roughly 1hz pulse from the first stage using these values, I just want to know how I got there.

Any help would be appreciated. If someone could show me their math so I can do it from now on that would be great

 

[Harald Kapp]

The 4536 can be operated with or without an internal prescaler (8 stages).depending on the state of the 8-bypass pin. If the prescaler is enabled, the signal to the counter is fin/256, The first stage of the counter divides by 2 so the output is fin/512. With your components fin=434Hz, so fin/512=0.85Hz which could explain your ibservation.

 

[kong]

I did get 434Hz, just didn't understand the rest. Are you saying the first stage of the counter divides by 512? 434/512=0.85Hz and that's the output I'm tapped into because I have the binary inputs set accordingly?

That makes sense. Very similar to 4060 expect in output stage capability.

 

[Harald Kapp]

Are you saying the first stage of the counter divides by 512

In fact the prescaler divides by 256, the first flipflop of the counter by 2. That makes for a total pf 512.
You can disable the prescaler using the 8-bypass pin of the 4536.

 

[kong]

So with the Bypass pin 'high' with the binary inputs all set to low, shouldn't I have my 434hz signal? Because the led lights but does not noticeably blink....when I take bypass low, I get a 1hz signal, now the counter should have 9 divider stages?

 

[Arouse1973]

You won't see 434Hz, the eyes can't pick this up. Think about 50Hz mains light bulbs and if you can see them flicker much.
Adam

 

[kong]

I now have it backwards for some reason....when the 8-bypass is 'high' I have a steady lit LED. But when it's high, it should be dividing my 434hz signal by 512, correct? That means I should have that 0.85hz and it should be blinking.

But it's the opposite; when 8-bypass is LOW it blinks, but wouldn't that mean that the 434hz is only divided by the first divider stage? That's what I have the binary input (DCBA) set for. LLLL on the input should equal the first divider stage connected to DECODE OUT. So, 434/2=217hz. So it should still be steady (since the eye can not register) but it's blinking. So essentially it's backwards.

Any idea? Thanks to both of you, by the way.

 

[kong]

Wait, actually I took a look at the truth table and everything checks out! Somehow I got it backwards in my head.

Since I'm here I also had a similar question regarding the 567 tone decoder. I posted about it here a couple weeks back but never got a reply. There is a calculator someone put up for it on google but I'm still having trouble with the bandwidth calculation.

BW= 1070 sqrrt Vi/ fo*c2

where: Vi <200mv C2=capacitance at pin 2 (uf)

I'm more curious how the math is done long hand than the actual values for a practical circuit. I'd just like to be able to work it out on my own. Here is the link to the datasheet: http://www.jaycar.com.au/images_uploaded/LM567.PDF

Thanks again!

 

[kong]

Figured it out. Amazing what a second try can achieve.