John Fields said:
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That doesn't make any sense.
Why don't you tell us what you're trying to do instead of how you
think you want to do it?
What I have at the moment which works fine, is a 3state buffer, 74HC541, and
4 2N5060 thyristors, when the 541 has a input it goes right though the
buffer.... the buffer then triggers the thyristor which latches on and stays
on. The voltages on the thyristor are also feed back into the 3state buffer
turning it off. Now should a input to the buffer rise again, nothing will
happen, and no latching will happen since the thyristors are isolated from
the input lines via the 541 buffer. This all works fine.......
Now what I want to do is do the same thing but with 1 IC, A latch IC. Now I
want the same to happen but without using seperate devices. I want to latch
a input line (like my thyristors does), then once one of the 4 latches are
on, I then want to isoltate the latches from the incomming inputs (like me
3state buffer does).
In anycase, the outputs of the buffer are going via a 4input OR gate and
then going to the 3state pin on the buffer. So when any input goes high,
that input is latched on and the buffer is disabled from any further inputs.
What I am not sure of is the 373 latch. If I have a input, normally to latch
it you have to pulse the clock pin to clock it into the latch. Normally
AFAIK if the clock pin stays high whatever is on the inputs appears on the
ouputs , and latched when the clock line goes low. (this is what the 374
looks to do).
I am not sure how the data and enable are working on the 373. I assume while
LE is high any data will be latched. Though the datasheet seems unclear if
its actually latched, or the outputs are just following the inputs (as it
would while the clock on the 374 were high).
I assume that on the 373 while LE is high, the data is latched, which looks
to me asif the outputs are just following the inputs until LE goes low,
which sounds like the clock on the 374. This looks like either a low or
high could be latched on the ouput while LE is high.
What im looking for is a latch which will only trip on and not latch off
also. A thyristor is idea, its a oneshot deal, once its on, its on. I want
my inputs on my "373" to latch on and stay on, then I want to keep those
latched outputs on, and disable the 373 form any further inputs. Though I
must point out that in the time it takes for the enable pin to go high, the
data may have changed on the inputs in which case I could loose my latch ON
and latch off.
I could draw the current circuit I have out, though its a bit more involved,
since the outputs of my buffer chip are actually feed back into the inputs.
I know this sounds daft, but im working with a bi-directional data bus which
has a special setup. And once the 1 input has been latched on, and then ORed
tot he enable, they are also ANDed together, so each of the 4 origonal input
are then set high, though this can casue the latch to latch the other 3
inputs on, so theres actually 4 zeners dropping the voltages on each of the
data lines, this is to give the enable pin a 5volt "head start" on the input
lines. I found that pulsing the enable high at the same time as the data
lines does not work, which is why I have to make sure the chip is disabled
before the "loop back" voltages trigger the other 3 latches.
I hope this makes sence, its a simple circuit, though theres a lot of parts
involved and im just trying to combine the latch and 3state buffers into 1
latch IC.......
Chris