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digital monostable?

Discussion in 'Electronic Design' started by cooldude, Aug 15, 2006.

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  1. cooldude

    cooldude Guest


    1) Is there any equivalent to monostable in fully digital electronics
    (logic gates)? I am trying to trigger a pulse (a set width) with a very
    narrow recovery time (in the range of 100ns or less) before the next.
    74LS221 seems to work although getting weird pulses (very short
    retrigger pulses) occasionally.

    2) And also whats the difference between the normal monostable and the
    precision ones? As the name suggested they'd be more precise

    3) Would 74HCT version will be more suitable although I read somewhere
    they are slower than the ls version.

  2. John Fields

    John Fields Guest

  3. Guest

    The digital way of generating a pulse having a well-defined width would
    be to count clock edges coming from a stable - usuually
    crystal-controlled - clock.

    The minimum increment in pulse width and the minimum recovery time is
    then the clcok period. With regular TTL and CMOS - 74F and 74ACT for
    instance - the maximum clock frequency is around 50MHz, giving a
    minimum incre,ent of 20nsec.

    If you use modern emitter-coupled logic ECLinPS or the like, you can
    go up to 500MHz and 2nsec.

    Motorola sell a digitially programmable delay generator - the MC100E195

    whose propagation dleay can be programmed to vary by at least 2nsec by
    changing a 7-bit word, which gives you a resoltion of about 20psec.

    I've used tapped delay lines to set up selectable pulse widths - the
    0.5nsec, 1nsec and 2nsec widhts were set up with lengths of RG174
    minature coaxial cable - and this approach doesn't have a minimum
    recovery time.

    The non-retriggerable 74121 and 74221 single and dual monostables have
    more precise and stable pulse widths than the retriggerable 74123 and
    74223 parts.

    The reason is obvious enough from the transistor-level design of the
    two different sorts of monostables, which was discussed in a Fairchild
    application note published in the early 1970's. I've not been able to
    find anything comparable on the web today.

    Check the data sheets.
  4. cooldude

    cooldude Guest


    Thanks for all the replies. There is no clock in my circuit so I can't
    use the time sampling approach.

    I heard about delay generator but still not sure how they could replace
    the "functional" nature of monostable. i.e triggering on edges of
    incoming signal with fix period (t).

    Any more light on that?

  5. Guest

    Please post your replies below the previous posts (bottom post) rather
    than above them (top posting). I've cut and pasted your reply to look
    as if it was bottom posted.

    If you want a counter-based digital monostable - which gives you the
    maximum control of your pulse width - you need to introduce a clock
    into your system. Farnell list a number of 50MHz clock modules, most of
    them costing around $5.

    The alternative is to used tapped lumped constant delay lines, which
    cost at least twice as much. Farnell list parts from C&D Technologies -
    which are real lumed constant delay lines, and ostensibly similar parts
    from Maxim/Dallas which - IIRR - are actually a number of monostables
    hooked up in series, which is a option that you might consider, since
    the recovery time for either one of a pair of monostables in series is
    going to be more than long enough to allow you to produce very nearly
    overlapping pulses.

    There is the problem that you have got to arrange to cover the gap when
    the first monostable has timed out and triggered the second, but the
    output of the second monstable hasn't yet reacted to the trigger. Three
    monostables would make this easy.

    The mechanism for capturing your trigger edge and turning it into a
    constant width pulse could be as simple as an RS flip-flop. The
    incoming edge flips the bistable from the Reset to to the Set state,
    and the Set output is fed into a delay line, and in due course
    propagates around to flip the bistable back to the Reset state.

    With an untapped delay line, the RS flip-flop is then held in the
    Reset state for the whole period of the delay, which isn't what you

    With a tapped delay line, you can gate the signal going into the delay
    line with the outputs from all the subsequent taps, which holds the
    duration of the pulse going through the delay line, and the recovery
    time, down to the tap-spacing.

    The details of the implementation are going to depend on what you are
    actually doing, and on what the triggerig pulse actually looks like -
    if it s a well-defined narrow pulse, you might be better off feeding
    that straignt into the delay line.

    Hope this helps. E-mail me - my address is real - if you don't want to
    publish the details of your application.
  6. Fred Bloggs

    Fred Bloggs Guest

    Why don't you skip all the bullsh_t generalities and abstractions and
    state the range of output pulswidths you want, the range of input
    trigger duty cycle and frequency, and the required response times!
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