Digital logic & CPU registers

[Nicholas Sherlock]

Hey all,

I'm designing an 8-bit CPU (With very slow clock!) on the excellent
freeware logic simulation package Logisim
(http://www.cburch.com/logisim). I'm not sure what the best design for
my registers will be. My ASCII art is useless, so you can find a diagram
of what I'm talking about here:

http://sherlocksoftware.org/registerdesigns.gif

In design 1, both the input (from the bus) and output (to the bus) of
the register are switched with tri-state buffers. To load a value from
the bus, you'd make "Input enable" for the specific register high, then
send a "Load clock" to that register.

I know that only one device can drive the bus at any time, but do I need
to protect the input that way? If not, design 3 shows the same thing but
with no tri-state on the input line. Loading a value from the bus simply
requires you to strobe the clock on the right register.

In design 2, there is a unified clock for all devices. An input enable
line chooses between recycling the value in the register and loading
from the bus. This is more complicated than I'd like!

In design 4, there is still a unified clock for all devices, but this
time two of the tri-states have been removed. The clock is and'ed with
the input enable line so that the value is only loaded when the enable
line and the clock are both high.

Which design should I choose? Or is there a better group to ask this
question in?

Cheers,
Nicholas Sherlock

 

[Deefoo]

Hey all,

I'm designing an 8-bit CPU (With very slow clock!) on the excellent
freeware logic simulation package Logisim
(http://www.cburch.com/logisim). I'm not sure what the best design for
my registers will be. My ASCII art is useless, so you can find a diagram
of what I'm talking about here:

http://sherlocksoftware.org/registerdesigns.gif

In design 1, both the input (from the bus) and output (to the bus) of
the register are switched with tri-state buffers. To load a value from
the bus, you'd make "Input enable" for the specific register high, then
send a "Load clock" to that register.

I know that only one device can drive the bus at any time, but do I need
to protect the input that way? If not, design 3 shows the same thing but
with no tri-state on the input line. Loading a value from the bus simply
requires you to strobe the clock on the right register.

In design 2, there is a unified clock for all devices. An input enable
line chooses between recycling the value in the register and loading
from the bus. This is more complicated than I'd like!

In design 4, there is still a unified clock for all devices, but this
time two of the tri-states have been removed. The clock is and'ed with
the input enable line so that the value is only loaded when the enable
line and the clock are both high.

Which design should I choose? Or is there a better group to ask this
question in?

Cheers,
Nicholas Sherlock

Supposing that In and Out connect to the same bus I'd go for design 4: I
don't see a need for tri-state input buffers, design 2 unnecessarily
complicates matters and you will probably need a kind of enable for loading
the register -> design 4.

Other good groups for this kind of issues are f.i. comp.lang.vhdl or
comp.arch.fpga

--DF