CRT Deflection circuit - sync pulses

[[email protected]]

Hello,

I'd like to understand the "guts" of the deflection circuit inside a
fixed-frequency display. I know the most monitors today are either
tri/quad sync, or truly multi-synchronous, but for learning purposes,
I'd rather start with a fixed-frequency display. I'm just learning the
basics of VGA timing (doing a video project on an FPGA), and I feel
that these answers would give me a more rock-solid grasp on what I can
and can't do with VGA.

At first, I thought that the horizontal deflection circuit would be
even simpler than a normal sawtooth relaxation oscillator. My thought
was that rather than using a "threshold" type device to trigger the
draining of the capacitor in the oscillator, we could just use the sync
pulse directly to turn a drain transistor on/off. But all the
information I've read on the net seems to suggest that the sync pulses
in some way add/subtract only slightly to the "normal" frequency. Can
someone clarify what's actually going on here? Perhaps there isn't one
correct answer (different companies, different method), but I'm
guessing that there's a common method used by most.

As for the vertical deflection, it should look like a "staircase",
right? Of course, there would be a sharp downward line after each
"staircase" for the vertical retrace. How is this waveform generated?
My initial guess, again, would be a simple integrator whose input was
the horizontal sync pulses. It would reset itself on each vertical sync
pulse.

However, this type of a setup would mean that the *length* of the
horizontal sync pulses would directly affect how much the picture was
vertically stretched. I'm not sure whether this is true or not.
Question: So long as the horizontal sync pulses are at the correct
frequency and are close to the correct length, does their *exact*
length in fact have a great effect on the picture? I'm a bit more into
the digital circuit world, so excuse the terminology, but another way
of asking the question might be: Is there some part of the deflection
circuit which is "edge-triggered" by the sync signal, or does the
actual pulse length of the sync signal matter? (I know that's kind of a
crude analogy since not all CRT's use digital circuitry - sorry)

If anyone can answer those questions, the next will be:

Tri/quad frequency monitors seem like a fairly straightforward
extension of fixed-frequency monitors, but how does the deflection
circuitry in *true* multi-synchronous CRT's work? I know a PLL is
involved, but what is the supporting circuitry? I've only just started
to become familiar with PLL's in general, so please excuse me if this
is fairly obvious. We were using PLL's in the context of sinusoids,
please let me know how they would be used to generate the sawtooth
signal we desire.

Of course, the threshold voltage (after which we want each sawtooth
pulse to end) would still be the same as with the fixed-frequency case.
After all, this is directly related to the size of the CRT screen. So
determining when to "reset" isn't hard. It's determining how fast the
sawtooth should rise (ie, how fast the beam sweeps horizontally) that I
don't understand (circuit-wise).

Thank you for your help !

Sean

PS - If anyone thinks that it would be better to a different group, let
me know.

 

[Ancient_Hacker]

Traditionally, TV sets have to be designed to handle noisy sync pulses.
So they use some kind of locked oscillator, nowdays a full-blown PLL,
where an integrator or capacitor smooths out the average frequency.

On a computer the sync pulses are cleaner than in a off-the-airwaves Tv
signal, but it's still advantageous to use a PLL or some kind of
stabilized and locked oscillator.

Tis is true of both vertical and horizontal syncs and sweeps.

The actual sweep generator has to deliver a linear ramp, in current,
not voltage, to the CRT deflection coils. This requires an impossible
voltage waveform (an infinte pulse at the beginning to instantly start
the current rising, this is usually omitted and the start of the sweep
is put a little bit off the left of the screen to not show this
glitch). The rest of the waveform is a trapezoidal pulse (in voltage)
which in an inductor generates a current ramp.

For the retrace, that requires a huge voltage pulse to sweep the
current quickly back to the left or top edge.

These funny signals are always generated by a very clever resonant and
diode-damped circuit, which is optimized to minimize the huge power
dissipation it would take to generate the retrace using normal methods.

I would NOT suggest you try to do one of these circuits on your own,
they're tricky and require parts that can take the high voltages and
currents.

 

[Jan Panteltje]

Hello,

I'd like to understand the "guts" of the deflection circuit inside a
fixed-frequency display.

When we talk CRT (not LCD), here you go:
A local oscillator is phase locked to the H sync pulse.
The oscillator drives a switch that basically puts a voltage
across the H defection coils for the duration of the line.
Because the coils are inductive, a linear rising current happens in the coils,
the resulting magnetic field sweeps the electron beam from left to right.
When the switch goes off at the end of the line, back EMF happens
and the current reverses (using a diode).
Use is made of resonance in this case.
To make a correction for the angle a capacitor is is series with
the H deflection coil, S correction, so angular speed is maximum in
the middle.

In the V deflection the inductance and frequency is so low that the coils
are driven by a normal totempole amp, the defection coil current is
measured by a small series resistor, and compared to a reference linear
sawtooth, also phase locked to the V sync.

In a VGA monitor there are many more corrections in the deflection system,
and perhaps the same system for H is used as I described for V here.
There is no 'staircase'.

When the frequency is higher, to get the same current in say half the time,
you would need double the voltage on the H deflection coil.

It is possible they use low inductance H deflection coils and a similar
drive as V, but I am not sure.
The days of a little diagram that comes with TVs or monitors are past..

My Samsung CRT is still working after being on 12/24 7 days/week, now for
5 years, so I have not looked at the circuit.
LCD is the future, but the picture is not as good as a good CRT.
Especially for video.
There are more better display systems in development.

 

[[email protected]]

Traditionally, TV sets have to be designed to handle noisy sync pulses.
So they use some kind of locked oscillator, nowdays a full-blown PLL,
where an integrator or capacitor smooths out the average frequency.

On a computer the sync pulses are cleaner than in a off-the-airwaves Tv
signal, but it's still advantageous to use a PLL or some kind of
stabilized and locked oscillator.

Tis is true of both vertical and horizontal syncs and sweeps.

I guess I'm still not 100% clear on the details of how the PLL is set
up for this task. Part of the problem might be that I'm only just
starting to learn about PLL's in general. But how would we take those
short square-pulse sync signals, feed it into a PLL, and then
eventually get a sawtooth output? And for the vertical deflection, how
would we use a PLL to eventually get that "staircase-like" output?

The actual sweep generator has to deliver a linear ramp, in current,
not voltage, to the CRT deflection coils.

Yes, I actually did realize that, but I guess I didn't word my post
quite right. If you like, add a voltage-controlled current source to
the output I described. Like you said down below, that might be very
impractical (ie, power-hungry, and stressful on components). But my
main interest is in generating the "shape" of the deflection waveform,
even if it wouldn't be a smart way to build a real CRT.

Thanks for the reply.
-Sean

 

[[email protected]]

Perhaps there is some way to make a voltage-controlled relaxation
sawtooth oscillator (where the threshold voltage for "resets" is
somehow adjustable by a voltage) and use a Type 2 PLL ? ie, the type
which only looks at the *edges* of the oscillator and reference input?
Just a guess.

 

[[email protected]]

Type 2 PLL ?

Apologize for the extra post, but I meant Type 2 phase detector

 

[Jan Panteltje]

Perhaps there is some way to make a voltage-controlled relaxation
sawtooth oscillator (where the threshold voltage for "resets" is
somehow adjustable by a voltage) and use a Type 2 PLL ? ie, the type
which only looks at the *edges* of the oscillator and reference input?
Just a guess.

It is relatively simple, charge a C, control the current source, use a
voltage comparator to trigger a flip flop that then discharges the C immediately.


I actually published one here a week or so ago.

----------------------------------------- +12V
| | |
[ ] [ ] R1 [ ]
| | |
| |</ e |
|---| PNP T2 | T3
| |\ c |--
T1 | --------\ | unijucntion transistor
| | |--
|---- d | |------------ B pulse out
----| JFET |---A |
|---- s | [ ]
| === |
Uin [ ] | C1 |
| | |
------------------------------------------- 0V



Capacitor C1 will be charged by constant current source T2.
The amount of current determines how fast T3 will trigger.

Current source T2 is controlled by T1

[] are resistors (European symbol).

Uin controls the frequency.

At point 'A' there is the linear ramp output.
The pulse out at point 'B' can be used as sample pulse in a phase discriminator.

Note that the amplitude of the ramp (sawtooth) is not depending on the frequency.

I have actually used UJT timebases in monitor, TV, and video camera design, 1968 or so.

You must feed 'A' into a high impedance.

 

[Peter Bennett]

As for the vertical deflection, it should look like a "staircase",
right? Of course, there would be a sharp downward line after each
"staircase" for the vertical retrace. How is this waveform generated?
My initial guess, again, would be a simple integrator whose input was
the horizontal sync pulses. It would reset itself on each vertical sync
pulse.

No - the vertical scan is a smooth sawtooth - the horizontal scan
lines are not truly horizontal - instead they slope downwards slightly
as they cross the screen.

 

[Jan Panteltje]

No - the vertical scan is a smooth sawtooth - the horizontal scan
lines are not truly horizontal - instead they slope downwards slightly
as they cross the screen.

Yoa yoa, I put a piece of paper under the right side of the set.

 

[[email protected]]

Thanks, Jan, for the schematic you included, and the explanation from
the previous post. That is what I was looking for. I had only been
exposed to PLL's as used in FM demodulation (with an analog multiplier
and a loop filter). After some more research and your posts, I think I
understand what is going on (hopefully).

As an aside, for VGA (not broadcasted television), do we really even
need the PLL? I'm not suggesting using a non-locked local oscillator,
I'm just suggesting using the sync pulses directly to dischage the
capacitor. I wouldn't think that there would be much noise on the sync
lines. (Not that I would do this if I was a commercial VGA monitor
producer, it's just another "what if" question).

Also, thanks to you and the other poster for clearing up my error about
the vertical deflection (ie, the bit I wrote about it looking like a
"staircase"). I hadn't noticed that when I first read my VGA
literature.

Now to apply this information to what I'm doing with VGA:

So if a CRT was built using the type of circuit you described, the
*duration* of the h-sync pulses shouldn't matter, so long as they are
long enough to bring the current in the inductor back to zero, right?
(or bring it negative, or whatever corresponds to the left of the
screen). If, for example, I continued to assert h-sync during the back
porch, I would expect the image to simply by shifted so that it went
*completely* to the left edge of the screen. (Exactly as if I didn't
include a back porch at all, and shifted the video data ahead by the
corresponding amount).

Perhaps that sounds tedious - something nobody would ever do. I guess a
more practical circumstance might be if my VGA driving circuit ran at a
frequency which wasn't an integer multiple of the desired dot clock.
Depending on how slow the clock was, one might be presented with
problems trying to keep within the timing specifications. It would be
nice to know what behavior to expect from the CRT if h-sync or v-sync
pulses were too long/short or at too high/low of a frequency. Hence my
reason for digging into the "guts" of the deflection circuitry.

And for a strictly fixed-frequency monitor, if I wanted to just use the
upper-left portion of the screen, could I just generate h-sync and
v-sync pulses twice as fast? (This would, of course, mean that I'm
sending the "wrong" sync frequencies to a fixed-frequency monitor. I'm
not sure whether there any any components that could fail by doing
this.)

Thanks again.
-Sean

 

[Jan Panteltje]

As an aside, for VGA (not broadcasted television), do we really even
need the PLL? I'm not suggesting using a non-locked local oscillator,

In theory at _one_ frequency, no PLL needed.
If the oscillator needs to lock over a high frequency a PLL circuit as I
did show has advantages.
But most important is, that if your sync was to interrupt, the scanning
of the CRT would stop, and the spot would burn in in the centre.
You want a picture even without input signal, my monitor then displays
a warning message about 'check signal cable'.
A CRT can burn in in a fraction of a second when all the energy goes to one
focussed spot on the screen.

Now to apply this information to what I'm doing with VGA:

So if a CRT was built using the type of circuit you described, the
*duration* of the h-sync pulses shouldn't matter, so long as they are
long enough to bring the current in the inductor back to zero, right?

The H sync time is specified in the spec, but it is _not_ the H sync
time that drives the H switch directly, that would be very dangerous,
some disturbance and the current in the horizontal output stage would
kill it.

The time ratio (on / off) of the H stage is set in the drive circuit.

-------- ------------ ------- H sync pulse, leading edge is used.
| | | |
- -

on
-------- ----------- ----- Horizontal drive
| | | |
-- --
off


black ---- ----
| | | |
------- --------- ----- blanking to CRT


||||||| |||||||||| |||| video luminance signal

(or bring it negative, or whatever corresponds to the left of the
screen). If, for example, I continued to assert h-sync during the back
porch, I would expect the image to simply by shifted so that it went
*completely* to the left edge of the screen. (Exactly as if I didn't
include a back porch at all, and shifted the video data ahead by the
corresponding amount).

Normally the ;leading edge of the H sync is used for trigger,
(phase aligned with a new scan), so the timebase circuit has some time to start.
If you make H too long in a composite signal it gets into the picture
as ultra-black.
If it is external sync you may notice very little, as normally only the
leading edge is used.

Perhaps that sounds tedious - something nobody would ever do. I guess a
more practical circumstance might be if my VGA driving circuit ran at a
frequency which wasn't an integer multiple of the desired dot clock.
Depending on how slow the clock was, one might be presented with
problems trying to keep within the timing specifications. It would be
nice to know what behaviour to expect from the CRT if h-sync or v-sync
pulses were too long/short or at too high/low of a frequency. Hence my
reason for digging into the "guts" of the deflection circuitry.

That depends on the PLL design.
These days there is (hopefully!) a frequency discriminator that checks for
a valid range (my monitor switches the HV and scanning off, if sync is out of range).
Else it would blow up.

And for a strictly fixed-frequency monitor, if I wanted to just use the
upper-left portion of the screen, could I just generate h-sync and
v-sync pulses twice as fast?

Simpler even, you use the same (correct) H and V frequency, but send the
info at double speed (double pixel clock) in the first line, and
wait the other half line time, and send the info in the second line you
have at double speed, etc, until you run out of lines.
This assumes your monitor can display those double high frequencies (detail).
This also shows you need _half_ the number of lines in your original!
On a 600 line height screen you have only 300 lines for half the picture.

(This would, of course, mean that I'm
sending the "wrong" sync frequencies to a fixed-frequency monitor. I'm
not sure whether there any any components that could fail by doing
this.)

So no need to do that.

 

[Ancient_Hacker]

Yoa yoa, I put a piece of paper under the right side of the set.

That's only on TV sets that did not pay the licensing fee for the
patent "straightening the picture by turning the yoke 1/525th of the
way to the left".

 

[Fred Bartoli]

Ancient_Hacker a écrit :

That's only on TV sets that did not pay the licensing fee for the
patent "straightening the picture by turning the yoke 1/525th of the
way to the left".

This patent is useless here where the hot thing is to tilt the yoke by
1/625th.

 

[Frithiof Andreas Jensen]

Yes, I actually did realize that, but I guess I didn't word my post
quite right. If you like, add a voltage-controlled current source to
the output I described. Like you said down below, that might be very
impractical (ie, power-hungry, and stressful on components). But my
main interest is in generating the "shape" of the deflection waveform,
even if it wouldn't be a smart way to build a real CRT.

Philips USED TO have a pdf-format book of application notes "Power Semiconductor
Applications" - but I cannot find it anymore amongst the corprat's "RAH RAH
RAH: Look How Great WE Are" Garbage on the web site! Maybe you have more luck
and/or patience.

 

[joseph2k]

In theory at _one_ frequency, no PLL needed.

In practice Yes, it is required to keep the horizontal and vertical blanking
from wandering all over the screen.

If the oscillator needs to lock over a high frequency a PLL circuit as I
did show has advantages.
But most important is, that if your sync was to interrupt, the scanning
of the CRT would stop, and the spot would burn in in the centre.

Not at all, the horizontal and vertical oscillators would free run as
designed. Moreover the anode high voltage is derived from the horizontal
sweep and no sweep translates sooner or later to no anode voltage.

You want a picture even without input signal, my monitor then displays
a warning message about 'check signal cable'.
A CRT can burn in in a fraction of a second when all the energy goes to
one focussed spot on the screen.

I have not had quick burn problems with my o'scopes. YMMV

They have to synchronize the horizontal oscillator, and for color TV gate
the chroma burst PLL. The other issues are internal to the display.

The H sync time is specified in the spec, but it is _not_ the H sync
time that drives the H switch directly, that would be very dangerous,
some disturbance and the current in the horizontal output stage would
kill it.

The time ratio (on / off) of the H stage is set in the drive circuit.

-------- ------------ ------- H sync pulse, leading edge is used.
| | | |
- -

on
-------- ----------- ----- Horizontal drive
| | | |
-- --
off


black ---- ----
| | | |
------- --------- ----- blanking to CRT


||||||| |||||||||| |||| video luminance signal

Please consider, that inductor (yoke) voltage is e = -L * di/dt. Thus a
very asymetrical current sawtooth is created by a voltage square wave that
is a bit asymmetrical. After the flyback pulse drives the yoke current to
the max -x position, the damper tube monotonically reduces the yoke current
to about zero. Then the horizontal output turns on and continues the sweep
from midscreen to the other edge. Then it cuts off and the resulting high
voltage spike reverses the current in the yoke very quickly.

Normally the ;leading edge of the H sync is used for trigger,
(phase aligned with a new scan), so the timebase circuit has some time to
start. If you make H too long in a composite signal it gets into the
picture as ultra-black.
If it is external sync you may notice very little, as normally only the
leading edge is used.

V-sync is not nearly so straight forward. Google for NTSC and look for a
thorough explanation of vertical sync; to be worthwhile it will include
"equalizing pulses". Now there is a can of worms for you.

That depends on the PLL design.
These days there is (hopefully!) a frequency discriminator that checks for
a valid range (my monitor switches the HV and scanning off, if sync is out
of range). Else it would blow up.

No.

Simpler even, you use the same (correct) H and V frequency, but send the
info at double speed (double pixel clock) in the first line, and
wait the other half line time, and send the info in the second line you
have at double speed, etc, until you run out of lines.
This assumes your monitor can display those double high frequencies
(detail). This also shows you need _half_ the number of lines in your
original! On a 600 line height screen you have only 300 lines for half the
picture.




So no need to do that.

See within.

 

[Jan Panteltje]

In practice Yes, it is required to keep the horizontal and vertical blanking
from wandering all over the screen.

That is actually not correct, in old TV vertical was just a hard synced blocking
oscillator, and V blanking was derived from the back EMF of the vertical out,
and H blanking form the line output transformer.
In such a case blanking 'cannot 'wander' if you are in sync.
Ever had an old TV with H and V frequency control?
I still have a portable that has it

Not at all, the horizontal and vertical oscillators would free run as
designed. Moreover the anode high voltage is derived from the horizontal
sweep and no sweep translates sooner or later to no anode voltage.

Maybe you should read again what the OP posted.
He sort of suggested originally that you could derive the ramp from the sync pulse.
This is possible, but there would be no scan when no sync, and burn in.
There is enough energy when scanning stops in the HV to burn in the tube before
the HV is also gone.
In the very old days when you switched the set off, the picture would
become smaller and smaller, and disappear in a point.
These days there is a deliberate blanking circuit to prevent this.

I have not had quick burn problems with my o'scopes. YMMV

We are talking TV, not scopes.
I have had CRT burn in in less then a second (and expensive case,
you need a new tube).
There is a safety normally when you do niot connect the scan coils,
but in the Philips set the safety did not work....
It is often just a bridge on the connector that allows voltage to
the H part.

They have to synchronize the horizontal oscillator, and for color TV gate
the chroma burst PLL. The other issues are internal to the display.

This is true, but incomplete.
As only the leading edge of H is used, no problem making it wider if
composite sync in.
In comp video in FBAS (was not the OP question) you would indeed lose the burst.

V-sync is not nearly so straight forward. Google for NTSC and look for a
thorough explanation of vertical sync; to be worthwhile it will include
"equalizing pulses". Now there is a can of worms for you.

Actually I had TV too on the scope
Not digital, Z input.

 

[joseph2k]

That is actually not correct, in old TV vertical was just a hard synced
blocking oscillator,

And how do you achieve that without the equivalent of phase locking?

and V blanking was derived from the back EMF of the
vertical out,

Not in the sets that i have schematics to. Nor does that invalidate the
fact that vertical blanking is transmitted as part of the NTSC, PAL and
SECAM formats.

and H blanking form the line output transformer.
In such a case blanking 'cannot 'wander' if you are in sync.
Ever had an old TV with H and V frequency control?
I still have a portable that has it

^ range

Maybe you should read again what the OP posted.
He sort of suggested originally that you could derive the ramp from the
sync pulse. This is possible, but there would be no scan when no sync, and
burn in. There is enough energy when scanning stops in the HV to burn in
the tube before the HV is also gone.
In the very old days when you switched the set off, the picture would
become smaller and smaller, and disappear in a point.

I remember those old sets, with a bright spot in the center as the anode
voltage decayed, it also spread out as focus voltage decayed which is
partly derived from anode voltage. They did not burn out either.

These days there is a deliberate blanking circuit to prevent this.

Nor did the old TVs from the late 1940s and early 1950s.

We are talking TV, not scopes.
I have had CRT burn in in less then a second (and expensive case,
you need a new tube).
There is a safety normally when you do niot connect the scan coils,
but in the Philips set the safety did not work....
It is often just a bridge on the connector that allows voltage to
the H part.



This is true, but incomplete.
As only the leading edge of H is used, no problem making it wider if
composite sync in.

Of equal importance is how much wider? all the way to line time?

In comp video in FBAS (was not the OP question) you would indeed lose the
burst.

A subset of the width issue.

Please explain equalizing pulses.

Actually I had TV too on the scope
Not digital, Z input.

See within.

 

[Jan Panteltje]

And how do you achieve that without the equivalent of phase locking?

Not sure what you mean here, normally the V osc would run slow, here is
a (simplyfied) diagram that I used for example in a design.

----------------------------------------- +12V
| | |
[ ] [ ] R1 [ ]
| | |--------------------------------
| |</ e | |
|---| PNP T1 | T2 |
| |\ c |-- [ ]
T1 | --------\ | unijunction transistor |
| | |-- | T3
| | |------------ B pulse out \| NPN
| |---A | |--===----- V sync
| | | [ ] //|
--->| | === | |
| | | | C1 | |
| | | | |
------------------------------------------------------------------------------ 0V
V hold poti



It _had_ to run slow, so it could be triggered before the restart,
When the V sync causes T3 to conduct the UJT trigger voltage level is slightly lowers, and
it triggers.
The trigger will _coincide_ with the V pulse, so is also phase locked.

Not in the sets that i have schematics to. Nor does that invalidate the
fact that vertical blanking is transmitted as part of the NTSC, PAL and
SECAM formats.

Yes, but only in composite video (FBAS).
There is a very simple and obvious reason why it _must_ be so: as the set runs free
(no station) you _still_ want the retrace of H (the flyback) and of V from bottom
to top, suppressed!
It is usually done by pulsing one of the anodes of the CRT with a signal derived from
a tap on the H output transformer, and somewhere from the V, the same circuit will
often also suppress the spot.

I forgot to point out that in modern KTVs the HV cascades (voltage multipliers) have considerable
capacitance too, with plenty of energy to do damage to the phosphors.

I remember those old sets, with a bright spot in the centre as the anode
voltage decayed, it also spread out as focus voltage decayed which is
partly derived from anode voltage. They did not burn out either.

Yes out of focus helps, normal BW sets had only about 15kV, color sets have
25kV.

Nor did the old TVs from the late 1940s and early 1950s.

Line burn in often happened, I have had a TV repair shop too, repaired thousands (no joking),
and line burn in I have seen too.
Even some old scopes (at about 4kV) had line burn in (remember DG57-34???).

Of equal importance is how much wider? all the way to line time?

Sure, more then half a line and you f*ck up the reverse H in the V in composite.

Please explain equalizing pulses.

Glad you asked.
We have to look a 3 different cases in case of sync:

1) Composite video (with composite sync).
2) Composite sync, 'S" input.
3) Separate H and V sync inputs (as in VGA 9 pole connector, the OP was talking about originally).

To start with 3 (simplest) most of the time the computer display is not interlaced, and
H and V can just be simple pulses, there need not even be a frequency lock (both derived
from the same clock etc).
And in case of interlace you need no 'egalisation' in fact.

This brings me to your question in case '1' and '2'.
The original reason for the egalisation pulses is dead simple, and almost never mentioned.
The intention was to have the (interlaced) receiver sync separator circuit
_as_simple_as_possible_.

The egalisation pulses are there to make sure the V integrator capacitor is charged in such
a way that the vertical retrace will start at half a line (625 / 2 = 312 1/2 in European PAL).

This system was designed so you could just with a simple differentiator and integrator split the composite sync.

 

[joseph2k]

And how do you achieve that without the equivalent of phase locking?

Not sure what you mean here, normally the V osc would run slow, here is
a (simplyfied) diagram that I used for example in a design.

----------------------------------------- +12V
| | |
[ ] [ ] R1 [ ]
| | |--------------------------------
| |</ e | |
|---| PNP T1 | T2 |
| |\ c |-- [ ]
T1 | --------\ | unijunction transistor |
| | |-- | T3
| | |------------ B pulse out \| NPN
| |---A | |--===-----
| |V sync
| | | [ ] //|
--->| | === | |
| | | | C1 | |
| | | | |
------------------------------------------------------------------------------
0V
V hold poti



It _had_ to run slow, so it could be triggered before the restart,
When the V sync causes T3 to conduct the UJT trigger voltage level is
slightly lowers, and it triggers.
The trigger will _coincide_ with the V pulse, so is also phase locked.

Hmmm, the equivalent of a PLL.

Yes, but only in composite video (FBAS).
There is a very simple and obvious reason why it _must_ be so: as the set
runs free (no station) you _still_ want the retrace of H (the flyback) and
of V from bottom to top, suppressed!
It is usually done by pulsing one of the anodes of the CRT with a signal
derived from a tap on the H output transformer, and somewhere from the V,
the same circuit will often also suppress the spot.

I forgot to point out that in modern KTVs the HV cascades (voltage
multipliers) have considerable capacitance too, with plenty of energy to
do damage to the phosphors.

Generating a reasonable steady voltage from microsecond wide pulses does
take some energy storage.

Yes out of focus helps, normal BW sets had only about 15kV, color sets
have 25kV.

Anode voltage and mean operating current have little to do with it. While i
have not serviced the sheer quantity of sets you have, i have had far more
problems with computer monitors having burn in. This seems to match my
understanding of the erosion model.

BTW i have a LCD monitor exhibiting the equivalent of burn in now.

Line burn in often happened, I have had a TV repair shop too, repaired
thousands (no joking), and line burn in I have seen too.
Even some old scopes (at about 4kV) had line burn in (remember
DG57-34???).

I saw line burn in on a scope only once, and only heard reports of it on
TV's.

Sure, more then half a line and you f*ck up the reverse H in the V in
composite.




Glad you asked.
We have to look a 3 different cases in case of sync:

1) Composite video (with composite sync).
2) Composite sync, 'S" input.
3) Separate H and V sync inputs (as in VGA 9 pole connector, the OP was
talking about originally).

To start with 3 (simplest) most of the time the computer display is not
interlaced, and H and V can just be simple pulses, there need not even be
a frequency lock (both derived from the same clock etc).
And in case of interlace you need no 'egalisation' in fact.

^equalization
See below.

This brings me to your question in case '1' and '2'.
The original reason for the egalisation pulses is dead simple, and almost
never mentioned. The intention was to have the (interlaced) receiver sync
separator circuit _as_simple_as_possible_.

No, it has to do with maintaining h-sync.

The egalisation pulses are there to make sure the V integrator capacitor
is charged in such a way that the vertical retrace will start at half a
line (625 / 2 = 312 1/2 in European PAL).

Equalization pulses bent the H sync so that it would be back in place at the
end of V sync. They occur on blank lines both before and after the V sync
series.

This system was designed so you could just with a simple differentiator
and integrator split the composite sync.

.
.
integrator .
neg polarity R . ramp build up
during v sync. comp sync ----------====-------------- V sync .
| |
| === C
| |
| ///
| |\
| differentiator | \
| | | C ___ __| \_____
-----| |---------------- H sync | /
| | | | /
| |/
[ ] R This edge is used (_also_ in
[ egalisation pulses!)
|
///


It must again be stressed that the comp sync does not need any egalisation
pulses if the display is not interlaced.
maybe some of you will remember the real start of computing, Motorola
max-board with 6845 CRT controller, you just made comp sync by xoring a H
pulse with a V pulse....... And the TV would be nicely locked.
And that twas even a common clock.

You forget it only displayed on even fields. It was not until the 6845A
that you could even try to use both vertical scans and even then it did not
work correctly.

I designed a video camera (vidicon) with 2 free running UJTs (as above) as
H and V oscillator, and xored the sync from these, then modulated on CH4
VHF in the sixties! WAY ahead of everybody
CCTV? I was first and wireless too!
Had it in the garden, battery operated, lasted 20 minute on nicads....

I haven't said it would work, but it does not meet specification. It was a
real PITA to meet spec in the tube days.

 

[Jan Panteltje]

BTW i have a LCD monitor exhibiting the equivalent of burn in now.

There was an interesting thread in comp.ibm.hardware.chips about the
'LCD" 'burn in' or storage effect, depending on the system and manufacturer
it sometimes helps to display white for say a night.

I saw line burn in on a scope only once, and only heard reports of it on
TV's.

First a correction, I think the tube was DG7-32
http://members.chello.nl/~h.dijkstra19/page3.html
It is the small one next to the big radar tube.....
This was my first oscilloscope 'design' (well I designed the power supply),
it was a tube oscilloscope, probably 1MHz bandwidth, no trigger, just 'sync'.
A year later I designed a transistor one, with video output transistors in
the deflection, real trigger, double timebase, on a printed ciruit with RTL logic!
But anyways, this DG7-32 burned in in the first hour or so...

^equalization
See below.


No, it has to do with maintaining h-sync.

Eh, yes and no.
In the olden days the time constant in the H PLL was really big, so the set
would just carry on at last freq if bad signal.
Then VHS came, and it had big timing errors in H due to the head position
changes, a big jump in H at the end of the frame (and missing lines at the
head switch-over).
So then sets got a much shorter timeconstant for H.
There was a time TV sets had 2 time constants.

Equalization pulses bent the H sync so that it would be back in place at the
end of V sync. They occur on blank lines both before and after the V sync
series.

Yes I know where they are.
Let's go a bit deeper:
If you xor the H with a longer V you get reversed H, but now the H starts posive,
and trhe differentiator in the sync separator deleivers a negatibve pulse, and
as we were using the negative pulse it is about 4.7uS late.
However the H PLL will adjust in few lines.

-- ------------ ------------ --
| | | | | | |
| | | | | | |
-- -- ------------- ---
|| ||
|| ||
|| ||
position of 'optional' egalisation pulses.

This system was designed so you could just with a simple differentiator
and integrator split the composite sync.

.
.
integrator .
neg polarity R . ramp build up
during v sync. comp sync ----------====-------------- V sync .
| |
| === C
| |
| ///
| |\
| differentiator | \
| | | C ___ __| \_____
-----| |---------------- H sync | /
| | | | /
| |/
[ ] R This edge is used (_also_ in
[ egalisation pulses!)
|
///


It must again be stressed that the comp sync does not need any egalisation
pulses if the display is not interlaced.
maybe some of you will remember the real start of computing, Motorola
max-board with 6845 CRT controller, you just made comp sync by xoring a H
pulse with a V pulse....... And the TV would be nicely locked.
And that twas even a common clock.

You forget it only displayed on even fields. It was not until the 6845A
that you could even try to use both vertical scans and even then it did not
work correctly.

Actually in the above drawing the V ramp is negative of course.....

I would have to climb in the attic, but I had interlace on a Z80 system
I designed with a 6845, but not sure it was 'A' or not.

Interlace is just a phase relationship between H and V, if you have a
Lissajous (spelling) display of 2 sine waves on the scope, you can phase adjust
so the lines do not overlap (pairing it is called).
The extra pulses cause the V integrator cap to charge a bit different, and
change the phase where the V triggers.
That is what was in my TV study book (no idea who wrote it, but it was good).

I think the H frequency does not _normally_ 'jump' during V sync (as in VHS).
It is just a matter of phase of V.
You can generate a 15 kHz sawtooth, and scope it.
Put the scope on a 20 ms trace, then you can change scope ms / division so
you see overlapping periods, or the sawtooth periods next to each other.
In one case you see 312.5 in the other 625 periods.
Is this right?
I think I tried this once, but maybe getting a bit rusty in this.
What do you think?

I haven't said it would work, but it does not meet specification. It was a
real PITA to meet spec in the tube days.

Well, I worked in the TV studio as engineer in the sixties, the old
sync generator had toobes, and very complicated, toobe flip flops....
yes it was full spec.... and a man height cabinet with forces air cooling.
When color came (1967 here) we got nice transistor sync generators....

All this interlock color carrier, 25 Hz offset, 8 frame editing sequence for PAL,
quadruplex.. amtec colortec color corrections....
But fact remains that you get color too with a 4,43MHz unlocked oscillator (like
in video games).
Just the interference pattern in the color areas then moves randomly on a BW set.....
But the sets (old and new) would eat almost anything you threw at it.