Chipcon modules CC1000PP

[Sebasto]

Hi

Currently I'm designing RF link using CC1000PP module from Chipcon. I set up
modules to Manchester data format and 19,2 kbps data rate. After calibration
I send data from microcontroler to transmitter with preamble and header. On
the receiver side I read data but in DCLK and DIO I have a lot of jitter.
There is little jitter ( not much ) when data is constant 1 or 0 or when
data is 0xAA, 0x55 etc. In data rate below 19,2 kbps I can read data
correctly, but above 19,2 kbps jitter is so big that I can't correctly read
data from the receiver.
Could you tell me what causes jitter in DCLK and DIO signal ?

Best Regards

Sebasto

sebastor(at)wp.pl

 

[Dana Raymond]

I have no experience with these devices, but have a suggestion... Could
jitter at the transmitting end be a problem? Also, if the jitter increases
as each individual bit is transmitted in time, then you may have a clock
domain issue of some sort, or a source of 60Hz noise being injected or
picked-up.

Totally a stab in the dark.
Dana Frank Raymond

 

[MarkyMark]

Sebasto,

There is a relatively obscure requirement to change the PLL loop bandwidth
when using bit rates of 38400 and above. If your data is 19200baud,
manchester encoded, then your bit rate is 38400.

Register @0x42 defaults to 0x25 for rates up to 19200bps, you need to set
this to 0x3f for your set up. This is not clear in the datasheet. The chip
does a poor job of modulation for higher speeds when using the default,
hence your RX jitter.

Regards Mark

 

[Grog]

Sebasto,

There is a relatively obscure requirement to change the PLL loop bandwidth
when using bit rates of 38400 and above. If your data is 19200baud,
manchester encoded, then your bit rate is 38400.

Register @0x42 defaults to 0x25 for rates up to 19200bps, you need to set
this to 0x3f for your set up. This is not clear in the datasheet. The chip
does a poor job of modulation for higher speeds when using the default,
hence your RX jitter.

Regards Mark

I was wondering if you were going to tell or not....

GtG
"It's not a bug, It's an undocumented feature"

 

[MarkyMark]

I was wondering if you were going to tell or not....

GtG
"It's not a bug, It's an undocumented feature"

Yeah well sometimes you just gotta be the bigger person. Sebasto could of
thrashed around for ages..... Luckily us west aussies are on top of things
(or is that underneath things). It's all relative according to that German
guy.

Stay Lucky

Mark

 

[Sebasto]

Sebasto,

There is a relatively obscure requirement to change the PLL loop bandwidth
when using bit rates of 38400 and above. If your data is 19200baud,
manchester encoded, then your bit rate is 38400.

Register @0x42 defaults to 0x25 for rates up to 19200bps, you need to set
this to 0x3f for your set up. This is not clear in the datasheet. The chip
does a poor job of modulation for higher speeds when using the default,
hence your RX jitter.

Regards Mark

Hi

Already traceiver workinkg preperly. I knew about TEST4 register, bad I made
some mistake in one of procedures :|

Regards

Sebasto