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Chipcon CC1020

Discussion in 'Electronic Design' started by christophe, Oct 26, 2006.

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  1. christophe

    christophe Guest

    I all,

    I'm working on the RF module Chipcon CC1020.
    I would like to know if somebody has a knowledge about the next point :

    I would test the processing signal time between the input signal (DIO
    pin) and the output (Antenna).
    My parameters are :

    Central frequency : 915MHz
    Data Type : NRZ
    Modulation : GFSK
    Power supply : + 3Vcc +/- 0.3Vcc
    Mode : Tx

    The input signal on the DIO pin is :

    Signal type : Square wave
    Amplitude : + 3Vcc
    Frequency : 12KHz

    Thanks for yours answers.

    Bests regards,

  2. joseph2k

    joseph2k Guest

    Sounds straight forward to me. What do you have for test equipment?
  3. vasile

    vasile Guest

    So, let see how you'll do it please.

  4. joseph2k

    joseph2k Guest

    A direct pll receiver should have less than a microsecond delay from 915 MHz
    input to analog output, superhetrodynes will be about 1 to 2 microsecond.
    Small enough to ignore for now.
    Use that to measure time dependant frequency and compare to the input data
    stream at the module terminals, expected mean delay for a completed symbol
    is about 1.5 symbol times (about 120 uS); for 12 KHz modulation rate the
    filter delays produce at least 40 uS delay and symbol time is 83 uS.
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