Can anyone simplifie this logic any more?

[Bondo86]

HERE's the logic I have.

Here's the truth table
ABC
000=0
001=7
010=-
011=2
100=0
101=-
110=8
111=2

I reduced a few OR gates using diodes but I can't think of anymore I could lose. Some people in class use quite a bit less gates than I do. This might be because I have a lot of segments used on the display though. I don't know. Thanks for any help.

 

[Laplace]

For the 010=- does the '-' signify segment 'g'? Same for 101? Is this supposed to be a segment display with tails or not? What minimization technique did you use to place diodes in the logic lines?

 

[Bondo86]

I should have specified that the dash(-) represented 'g'
101 & 010 do both produce the g segment. Tails don't matter, and I didn't put one on the 7. The diodes were put there to take out 12 OR gates by sharing gates with repeated numbers. The two zeros, two dash marks and the two twos.

 

[Laplace]

The first thing needed is a segment truth table in order to generate the Karnaugh maps for each segment. Now if I did the attachment correctly it shows that some segments are driven by the same logic conditions so the segments can be tied together and driven by the same gates. Also when generating a minterm for one segment and the same minterm is used for another segment, it should only be generated once. That may be a consideration when selecting minimizations for the K-maps. So exactly how did you minimize your K-maps in order to come up with the gate arrangement presented initially?

 

[Bondo86]

Well.... I had no idea how to make a k-map for a 7 segment display. I did some googling and tried to think of ways, but my ways didn't help any minimizing. I was going about it all wrong. You would think they would have talked about this in school but alas nothing was said. I appreciate your help more then you know. After seeing the k-map I can see why people invert the inputs now. I'll get working on this. Thanks.