Buffer to delay a signal

[Lizwi]

Hi

I am simulating a delay line time to digital converter, I have been able to simulate a counter TDC,

How do I create a buffer with delay in Verilog HDL? I am trying to simulate what is in the attachment. Please help.

 

[danadak]

https://www.ece.ucdavis.edu/~bbaas/281/notes/Handout.verilog3.pdf

Regards, Dana.

 

[Lizwi]

What am I doing wrong here, I want to get a pattern on the timing diagram attached. The buffers are there but they don't seem to delay the signal.

 

[Harald Kapp]

You need to zoom in much more into this area:

The buffers in your simulation probably have a delay in the sub-ns range. The dashed lines are 10 ns apart. You can't see the small delay in that resolution.

Another possibility is that the RTL compiler "optimizes" the design, recognizing that the output signals of the buffers are identical and therefore removes the buffers from the simulation. You may (or may not) have an option to turn off such an optimization in the simulator's settings.

Note that in a real circuit the delay may vary considerably depending on where on the chip the buffers are palced and how long the interconnects are.

 

[Harald Kapp]

Delay a signal in VHDL -> link.
Problem of "overoptimizing" compiler -> link.

 

[Alec_t]

The buffers are there but they don't seem to delay the signal.

Does your sim software allow for specifying the buffer delay amount?