Battery-backed SRAM: how?

[Thierry Nouspikel]

Hi there,

I need to back a low-power SRAM with a coin battery, so that its
contents remain unaltered while power is off.

The power part it easy: I'll just connect both the battery and the
regular +5V power to the Vcc pin of the SRAM, each via a diode (e.g.
1N4148).

But I have more problems with the CS* pin. This SRAM has no active-low
standby pin, so the only way to put it in low-power standby is to hold
CS* high when power is off. This could be done by connecting CS* to the
Vcc pin via a 4.7K resistor.

However, how am I to drive CS* during normal operation? If I use a
standard TTL gate, it will drain the battery through the resistor when
power is off.

I though of a complicated scheme using a PNP and a NPN transistor, but
I'm sure there must be an easier way. For instance, would a 74HCT do the
job or will it also drain the battery?

Thanks for your help,
Thierry

 

[John Larkin]

Hi there,

I need to back a low-power SRAM with a coin battery, so that its
contents remain unaltered while power is off.

The power part it easy: I'll just connect both the battery and the
regular +5V power to the Vcc pin of the SRAM, each via a diode (e.g.
1N4148).

But I have more problems with the CS* pin. This SRAM has no active-low
standby pin, so the only way to put it in low-power standby is to hold
CS* high when power is off. This could be done by connecting CS* to the
Vcc pin via a 4.7K resistor.

However, how am I to drive CS* during normal operation? If I use a
standard TTL gate, it will drain the battery through the resistor when
power is off.

I though of a complicated scheme using a PNP and a NPN transistor, but
I'm sure there must be an easier way. For instance, would a 74HCT do the
job or will it also drain the battery?

Thanks for your help,
Thierry

Just use an HC or HCT gate, powered off the ram battery-backed Vcc.
You'll need to have a clean powerup/down RESET signal... use one of
those Maxim or whatever reset sense chips. The gate does the logic to
pass the cs signal, but force it false when reset is true.

I've tested lithium batteries from units that have been in the field
for up to six years, using circuits like this. So far, we see no
systematic sign that the older batteries have any less capacity than
fresh ones. These are, of course, from instruments that are powered up
most of the time once they are installed in the field.


John

 

[Nico Coesel]

Hi there,

I need to back a low-power SRAM with a coin battery, so that its
contents remain unaltered while power is off.

The power part it easy: I'll just connect both the battery and the
regular +5V power to the Vcc pin of the SRAM, each via a diode (e.g.
1N4148).

I though of a complicated scheme using a PNP and a NPN transistor, but
I'm sure there must be an easier way. For instance, would a 74HCT do the
job or will it also drain the battery?

You could look into an FRAM from Ramtron. These devices are
non-volatile without the need of a power source. You can't run a
program from them though.

 

[Spehro Pefhany]

Not that I want it, but why can't you run a program from FRAM ?

You *could*, but the 1.0E10 read endurance, as on the FM1808 32K x 8,
might be pretty limiting.. as in a lifetime measured in single or
double-digit hours.

Best regards,
Spehro Pefhany

 

[Frank Bemelman]

You *could*, but the 1.0E10 read endurance, as on the FM1808 32K x 8,
might be pretty limiting.. as in a lifetime measured in single or
double-digit hours.

I forgot that. Now I remember Still have some samples here, tested
and evaluated them as okay, but never designed them in.

 

[Thierry Nouspikel]

You could look into an FRAM from Ramtron. These devices are
non-volatile without the need of a power source.

Actually, my initial post was lacking details: I'm using a dual-port
SRAM.
Unfortunately, I don't think there are any dual-port EEPROMs around, but
I'd love to be proven wrong...

Thierry

 

[Aubrey McIntosh]

I use a FM1608 (the low endurance part) in a 68HC11EVB in place of the
EPROM. It's a magic part that everyone should know about. The board
boots and runs from this device. I even (gasp) have the stack in this
part. I know that I am consuming 'permanence' like crazy in the stack
area, but I don't need a permanent stack. This device has been
configured since 2000, and seems to be reliable.

 

[Dana Raymond]

There are chips that are specifically designed for this task Thierry. I
would reccomend you check them out (Dallas Semi, for instance). They do a
few more things that the appicaltion requires, such as:

1) Precise voltage detection and battery switchover. Earler switchover
prevents data corruption.
2) CS is driven through the chip (CSin, CSout) so that the RAM will be
guaranteed in lowest power mode.
3) If the power begins to fail during a CS cycle, the chip will allow the
cycle to complete before locking out the RAM.
4) To prevent power up glitches from affecting RAM contents, a specific
sequence is required to enable the chip.
5) Dual battery versions allow for inteligent management of both batteries.
6) Battery fail output indicator pins can drive leds or signal a micro that
the battery must be changed, etc.
7) Some chips have built-in address decoders allowing multiple RAMs to be
backed-up using only one CS.

I used to do the supercap/schottky diode/100R resistor thing with static
RAMs years ago and it was difficult for me to eliminate data corruption
until I switched over to using these chips designed for the purpose. Based
on decades of experience, I'd suggest you do the same.

http://para.maxim-ic.com/compare.asp?Fam=NVCntrlr&Tree=uPSupervisors&HP=Supe
rvisors.cfm&ln=

Hope this helps.
Dana Frank Raymond

 

[Dana Raymond]

When showing battery backup circuitry you need to see both /CS control and
VDD SRAM supply. Your VBat may, or may not, be sourced by Vcc. I can't tell.

Take your backup battery and protect it with a diode (schottky if battery
life is important). This is VBat. Source VBat with Vcc though a resistor -
The backup battery will then not be used when power is up.

VBat goes to SRAM power. Decoupling, etc.

VBat goes to /CS via a resistor. /CS is also pulled down by a 2N7002 FET.
The logic level gate is driven by your TTL signal (except inverted).

Now, you need to consider a few things, OK?

1) Many SRAMs operate at higher power when /CS is asserted. Thats means
higher power consumption since /CS is always active instead of only for the
actual bus cycle.
2) You will not be able to avoid data corruption unless you also incorporate
a Vcc voltage monitor that somehow disables SRAM cycles.

Also, you are driving /CS via TTL through a signal diode. Is the SRAM's /CS
VIH LOWER than (TTL Voh 3.6V - 0.7V = 2.9V)? That could be a proble,. Now,
if you were using CMOS (74HC) instead...

$25!!! How many SRAMS are you using? It should only cost a few dollars to
fully protect a single SRAM.

Dana Frank Raymond

 

[Dana Raymond]

Take a look at Dallas' DS1321, a 16 pin device that supports 2 independant
/CS lines (mode pin floating).
Digikey has stock at about $10. Or TI's DQ2201SN for less than $4 a piece (2
needed).

The DS1321 can also replace your 5V POR circuit. It generates a 200mS POR
imterval for external use.

Hope this helps.
Dana Frank Raymond