Bart said:
Hi All,
I've successfully cascaded 4 of the 74LS193 binary up-down counter chips
to count up to full, off a 555 oscillator. Now I'm stuck. I want the
circuit to count to full and then count back down to zero and continue
this cycle endlessly. I've googled my flanges off and can't find a circuit
where this is done. The datasheet brags that this is the advantage of this
chip that it can be cascaded without additional elements so I was sure I'd
find where someone had done this before but I'm googled out.
Any help is greatly appreciated,
Bart
Bart,
That 74LS193 are weird old things. You will have found that they are
cascaded by connecting the carry output to upcount of the next chip and the
borrow to the downcount. So this counters may by internally synchronous, all
the rest is asynchronous. You will draw the same conclusion when you realise
that the driving clock(s) are connected only to the first counter. To
achieve your goal we'll have to open the toolbox of the old asynchronous
designers with the suitable logic and a bunch more or less dirty tricks.
Mentioned by others already is the input circuit to switch up/down and lead
the clock to the desired input. For your and mine convenience I draw it
below.
__
Setup -----| | __
|& |o-+-----| |
+--|__| | |& |o---Cup
| | +--|__|
+--+ +-+ |
\ / |
X |
/ \ |
+--+ +--+ |
| __ | |
+---| | | | __
|& |o-+-)--| |
Setdown-----|__| | |& |o----Cdo
+--|__|
|
|
clock |
--------------+
created by Andy´s ASCII-Circuit v1.24.140803 Beta
www.tech-chat.de
One 74LS00 will do the job. Remind that the trigger has active low inputs.
So Setup and Setdown are normally high and you select by pulling the
corresponding input low for a short time. Trying to set both at the same
time will block the counter. You can't count up and down at the same time
anyway.
To find a way to make the counter switch automatically, you'll have to look
at the datasheet of the LS193. If you don't have it find it, download it and
print it out. You can't do any serious work without it. The datasheets
contains pulse diagrams. (At least mine - Texas - does.) You can see that,
when counting up, the Carry appears just half a clockcycle before the
counter rolls over. The first three counters in the row simply feed through
the carry. It's on the trailing (rising) edge of that pulse of the fourth
counter we want to act. That's to say the whole countercircuit should not
roll over but counts down one step and switches to countdown mode. The
latter can be achieved by presenting a short negative pulse to the Setdown.
To count one down at the same time can be achieved by presenting 1111 1111
1111 1110 to the parallel load inputs and a short negative pulse to the Load
input. Now that small negative going pulse can be made by a monostable. Half
a LS221 will do the job. Use the positive edge trigger (B) input to connect
the carry to and the inverted Q output to drive both Setdown and Load. The
pulse length should be shorter then half a clock cycle but long enough to
get the load done. One us (microsecond) will do. You may find glitches on
the counter outputs which can be considered "normal" when you use
asynchronous resets or loads. No need to say you'll need the datasheet of
the 74LS221.
When counting down, the Borrow on the last LS193 appears when the counter
reached all zeroes. We cannot do the load-trick as we have the parallel load
inputs in use already, so we need something else. That else is another
monostable, triggered on the rising edge of the borrow. This time we need
the inverted Q output to trigger the Setup and the Q output to reset the
counter as a whole. The disadvantage is that the all zeroes state resides
twice the normal time, so two clockpulses.
You can overcome this disadvantage at the cost of some extra hardware and
glitches but I consider this story long enough for the moment.
petrus bitbyter
