I have this comparator circuit with hysteresis. I have designed it for 0.2V hysteresis and it works fine. But when I design it for higher hysteresis like 1V it output is not correct. The supply voltage for opamp is (12,0). The ref voltage is 5.1V for both cases. Value of R1 is 1K and Rf is 56.4k...
I am trying to simulate a circuit in ORCAD including basic inverting operational amplifier as attached.
Where R1 = 1k, R2 = 250k and input is 10mV. The opamp used is LM124. The output should be -2.5V but when I simulate it the output is -167.68mV. What can possibly be the reason of that much...
The diode Dg is used to introduce delaty in rise of Vgs to Vplateau because if Vgs reaches
plateau before current decays in Rgd,Cgd branch then it will cause overshoot, mosfet will
turn on momentarily and inrush current will flow. What do you think?
I have attached an undervoltage lockout circuit. i hav simulated it for a continuous square wave but it works only for first positive cycle. Whats the reason for that?