Ban wrote...
Your FET is too wimpy for the high currents you want to conduct.
47mOhms means that with 100A you have already 4.7V across the
transistor, which will now develop 470W of dissipation, which
instantly will increase the channel resistance and heat up even
more. I suggest a couple of paralleled IRL3716 which have only
4.8mOhms Rds.
http://www.irf.com/product-info/datasheets/data/irl3716.pdf
A logic-level FET is a good choice if one wants to use the FET's
transconductance to establish a constant current electronic load.
An IRL3716 would be a good choice for a 100A load, because 100A is
close to the current at which it has zero transconductance tempco,
with about a 2.9V gate voltage for Vds = 15V, see fig 3. I'd add
a source degeneration resistor to better establish the current at
different drain voltages. For example, a 0.02-ohm low-inductance
resistor would drop 2V at 100A, and a 5.0V gate drive would bias
the IRL3716 to sink about 90A for 8V to 100A for 15V on the drain.
One can adjust the gate pulse voltage to trim the 100A current.
These FETs may be hard to get in the TO-220 version (the surface-
mount versions, which have less thermal capability, are in stock),
so an IRF IRL1404 or IRL2505 (Vgs = 3.8V), or a Fairchild FDP7045L
(Vgs = 3.3V) can be considered instead.
Done this way, with the battery current dissipated mostly in the FET,
each battery-test pulse has to be short, limited by the thermal mass
of the MOSFET. The thermal mass parameter isn't given directly on
the datasheet, but for a quick part search one can eyeball the FET's
maximum Pd spec, which is usually on the front page. A low thermal
resistance is required for a high Pd, and this usually implies a high
thermal mass. To complete the calculation for the selected FET, one
refers to the Maximum Effective Transient Thermal Impedance curves,
e.g., fig 11 for the IRL3716. For example, let's assume our FET has
about 10V across its D-S terminals during our 100A pulse, which would
be 1kW dissipation. Assuming a 150C junction temp rise, we calculate
a maximum allowed Thermal Response ZthJC = dT/P = 150C/1kW = 0.15C/W,
and examining the single pulse curve, we see that this corresponds to
a maximum pulse duration of about 500us. This is consistent with the
figure 8 Maximum Safe Operating Area plots.
These have a very high gate capacitance, so your gate driver should
be able to source/sink a couple of amps to avoid long switching times.
Right, we're talking Ciss into the 5nF territory, which requires a
0.25A gate current for a 0.1us switching time (for a 5V pulse). A
wimpy 10mA gate-drive capability, as from a CMOS 555 timer, could
result in a rather slow 2.5us to 5us switching time. That's 1 to 2%
of a say 250us test pulse.
