O
OBones
- Jan 1, 1970
- 0
Hi all
I've got two lines: 1 data, and 1 clock
When the clock goes down to up, the data is ok. What I want to do is to
have a logic 1 when the data line was 1 for the last two clock "low to
high" transitions. If the last two states were not 1, then the output
must be a logic 0.
At first I though of using two D-Type flip flops (74AC74) in cascade
configuration with the Q output of the first one being the input of the
second one. Then I "AND" the two Q's and I get the logic 1 I'm looking for.
__
.------------| \
.--o--. | .--o--. |08 )-
Dta -----|D S Q|--+--|D S Q|---|__/
-|> | -|> |
Clk ---+-|C R Q| .-|C R Q|
| '--o--' | '--o--'
'-----------'
(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)
However, the room I have on the board is very scarce and I would like to
take advantage of the 4 schmitt trigger inverters I have in a 74AC14
chip. This chip is used along with 3 out of 4 AND gates in a 74AC08 to
create the above mentionned data line.
So here is what I have left:
1 AND and 4 Schmitt NOT.
Is there a way to create a "1 bit memory" using schmitt trigger
inverters? The schmitt trigger inverters could be replaced by regular
inverters if need be. They are used to generate the Data line like this:
|\ __
Q1 o---|S>O------| \
|/ |08 )---.
|\ .---|__/ | __
Q2 o---|S>O--' '--| \
|/ |08 )- Dta
__ .--|__/
Q3 o-------------| \ |
|08 )---'
Q4 o-------------|__/
(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)
I hope I'm clear enough in my explanations, please do not hesitate to
ask questions if need be.
Thanks a lot for any help.
Cheers
Olivier
I've got two lines: 1 data, and 1 clock
When the clock goes down to up, the data is ok. What I want to do is to
have a logic 1 when the data line was 1 for the last two clock "low to
high" transitions. If the last two states were not 1, then the output
must be a logic 0.
At first I though of using two D-Type flip flops (74AC74) in cascade
configuration with the Q output of the first one being the input of the
second one. Then I "AND" the two Q's and I get the logic 1 I'm looking for.
__
.------------| \
.--o--. | .--o--. |08 )-
Dta -----|D S Q|--+--|D S Q|---|__/
-|> | -|> |
Clk ---+-|C R Q| .-|C R Q|
| '--o--' | '--o--'
'-----------'
(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)
However, the room I have on the board is very scarce and I would like to
take advantage of the 4 schmitt trigger inverters I have in a 74AC14
chip. This chip is used along with 3 out of 4 AND gates in a 74AC08 to
create the above mentionned data line.
So here is what I have left:
1 AND and 4 Schmitt NOT.
Is there a way to create a "1 bit memory" using schmitt trigger
inverters? The schmitt trigger inverters could be replaced by regular
inverters if need be. They are used to generate the Data line like this:
|\ __
Q1 o---|S>O------| \
|/ |08 )---.
|\ .---|__/ | __
Q2 o---|S>O--' '--| \
|/ |08 )- Dta
__ .--|__/
Q3 o-------------| \ |
|08 )---'
Q4 o-------------|__/
(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)
I hope I'm clear enough in my explanations, please do not hesitate to
ask questions if need be.
Thanks a lot for any help.
Cheers
Olivier