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Storing bits using schmitt trigger inverters

O

OBones

Jan 1, 1970
0
Hi all

I've got two lines: 1 data, and 1 clock
When the clock goes down to up, the data is ok. What I want to do is to
have a logic 1 when the data line was 1 for the last two clock "low to
high" transitions. If the last two states were not 1, then the output
must be a logic 0.
At first I though of using two D-Type flip flops (74AC74) in cascade
configuration with the Q output of the first one being the input of the
second one. Then I "AND" the two Q's and I get the logic 1 I'm looking for.

__
.------------| \
.--o--. | .--o--. |08 )-
Dta -----|D S Q|--+--|D S Q|---|__/
-|> | -|> |
Clk ---+-|C R Q| .-|C R Q|
| '--o--' | '--o--'
'-----------'

(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)


However, the room I have on the board is very scarce and I would like to
take advantage of the 4 schmitt trigger inverters I have in a 74AC14
chip. This chip is used along with 3 out of 4 AND gates in a 74AC08 to
create the above mentionned data line.
So here is what I have left:
1 AND and 4 Schmitt NOT.
Is there a way to create a "1 bit memory" using schmitt trigger
inverters? The schmitt trigger inverters could be replaced by regular
inverters if need be. They are used to generate the Data line like this:

|\ __
Q1 o---|S>O------| \
|/ |08 )---.
|\ .---|__/ | __
Q2 o---|S>O--' '--| \
|/ |08 )- Dta
__ .--|__/
Q3 o-------------| \ |
|08 )---'
Q4 o-------------|__/

(created by AACircuit v1.28.5 beta 02/06/05 www.tech-chat.de)

I hope I'm clear enough in my explanations, please do not hesitate to
ask questions if need be.
Thanks a lot for any help.

Cheers
Olivier
 
J

Joerg

Jan 1, 1970
0
Hello Oliver,
Is there a way to create a "1 bit memory" using schmitt trigger
inverters? ...

Yes, I do this all the time. Can't draw an ASCII schematic but it's
simple: Take two resistors of 1M or more, depending on the speed you
want from that 1bit memory. For really high toggle speeds you can dip
into the kohm range. Connect R1 to the output of U1A and to the input of
U1B. Connect R2 to the output of U1B and the input of U1A. That's it.

If you need the 1bit memory to come up in a defined state at power up
you'd have to spring for another FET, a resistor and a cap. Hang a
seconds FET if you have to make another 1bit memory.

Now you can play all kinds of tricks such as using an input cap to make
it DC insensitive, and so on.

Regards, Joerg
 
O

OBones

Jan 1, 1970
0
Joerg said:
Hello Oliver,



Yes, I do this all the time. Can't draw an ASCII schematic but it's
simple: Take two resistors of 1M or more, depending on the speed you
want from that 1bit memory. For really high toggle speeds you can dip
into the kohm range. Connect R1 to the output of U1A and to the input of
U1B. Connect R2 to the output of U1B and the input of U1A. That's it.

If you need the 1bit memory to come up in a defined state at power up
you'd have to spring for another FET, a resistor and a cap. Hang a
seconds FET if you have to make another 1bit memory.

Now you can play all kinds of tricks such as using an input cap to make
it DC insensitive, and so on.

Thanks for this info, I'll dig into that.
Considering the explanation of what I want to do, does this usage of the
schmitt triggers sound plausible to you?
 
K

Keith Williams

Jan 1, 1970
0
Is there a way to create a "1 bit memory" using schmitt trigger
inverters? The schmitt trigger inverters could be replaced by regular
inverters if need be. They are used to generate the Data line like this:

Sure. Bias the schmitt trigger in the hysterisis zone. Give it a kick above
the hysterisis to get it to a '1' and below for a '0' (or inversion thereof).
When it settles back to its bias point it will retain that level. One can make
bistable, monostable, or astable multivibrators using a schmitt triggers biased
appropriately.
 
J

Jim Thompson

Jan 1, 1970
0
Sure. Bias the schmitt trigger in the hysterisis zone. Give it a kick above
the hysterisis to get it to a '1' and below for a '0' (or inversion thereof).
When it settles back to its bias point it will retain that level. One can make
bistable, monostable, or astable multivibrators using a schmitt triggers biased
appropriately.

But certainly NOT good engineering practice. Reliability in a
production environment would be zilch.

...Jim Thompson
 
K

Keith Williams

Jan 1, 1970
0
But certainly NOT good engineering practice. Reliability in a
production environment would be zilch.

Sure. My intention was to point out that these are all really the same
circuits, biased differently. A device designed as a "schmitt trigger" won't
have a wide, nor stable (predictable), hysterisis zone to so easily bias.
They'll oscillate rather well though.
 
J

Jim Thompson

Jan 1, 1970
0
Sure. My intention was to point out that these are all really the same
circuits, biased differently. A device designed as a "schmitt trigger" won't
have a wide, nor stable (predictable), hysterisis zone to so easily bias.
They'll oscillate rather well though.

;-)

...Jim Thompson
 
O

OBones

Jan 1, 1970
0
Jim said:
But certainly NOT good engineering practice. Reliability in a
production environment would be zilch.

I understand that. The thing is that I have the space for two SOIC14
chips. So maybe I should look into changing the gates I'm using to get
the "data" line to be able to use only two chips. Does anyone have an
idea on how to do that?
I'll think about it too, but just in case someone has ideas.
 
J

Joerg

Jan 1, 1970
0
Hello Oliver,
Considering the explanation of what I want to do, does this usage of the
schmitt triggers sound plausible to you?

Well, I only explained how to make a 1bit register since you asked for
that. It would require some thinking but most likely you can do a
lock-out if your "data valid over two clocks" is violated, using just
Schmitt inverters. However, since that usually requires some added RC
the space of the extra parts might be the same as one more chip. You can
get logic such as CD4000 and 74HC in TSSOP which is really small.

Regards, Joerg
 
Keith Williams skrev:
Sure. My intention was to point out that these are all really the same
circuits, biased differently. A device designed as a "schmitt trigger" won't
have a wide, nor stable (predictable), hysterisis zone to so easily bias.
They'll oscillate rather well though.

how about:
Assuming the gates in a package track, make an rc oscillator with one
of the
schmitt triggers in the package and lowpass filter the output, you now
have a
dc voltage right in the middle of the "eye" ?

-Lasse
 
J

Joerg

Jan 1, 1970
0
Hello Oliver,
I understand that. The thing is that I have the space for two SOIC14
chips. ...

Consider TSSOP. They are way smaller than SO.

Regards, Joerg
 
K

Keith Williams

Jan 1, 1970
0
Keith Williams skrev:


how about:
Assuming the gates in a package track, make an rc oscillator with one
of the
schmitt triggers in the package and lowpass filter the output, you now
have a
dc voltage right in the middle of the "eye" ?

Good idea, but I prefer not to rely on unspecified parameters. My bet is that
it would take a pile-o-money to get the necessary parameters specified.
 
J

Joerg

Jan 1, 1970
0
Hello Oliver,
But way harder to solder manually...

Yes. For these you really need to consider an investment into hot air
soldering equipment. Although I did solder them successfully with a
Weller ETS tip. Easy on the coffee before trying that ;-)

Regards, Joerg
 
R

Rich Grise

Jan 1, 1970
0
Hi all

I've got two lines: 1 data, and 1 clock
When the clock goes down to up, the data is ok. What I want to do is to
have a logic 1 when the data line was 1 for the last two clock "low to
high" transitions. If the last two states were not 1, then the output
must be a logic 0.
At first I though of using two D-Type flip flops (74AC74) in cascade
configuration with the Q output of the first one being the input of the
second one. Then I "AND" the two Q's and I get the logic 1 I'm looking for.
[ASCII schem. snipped]

However, the room I have on the board is very scarce and I would like to
take advantage of the 4 schmitt trigger inverters I have in a 74AC14
chip. This chip is used along with 3 out of 4 AND gates in a 74AC08 to
create the above mentionned data line.

Just put the whole schmear in one little CPLD or FPGA or something.

Good Luck!
Rich
 
J

Jim Thompson

Jan 1, 1970
0
Hi all

I've got two lines: 1 data, and 1 clock
When the clock goes down to up, the data is ok. What I want to do is to
have a logic 1 when the data line was 1 for the last two clock "low to
high" transitions. If the last two states were not 1, then the output
must be a logic 0.
At first I though of using two D-Type flip flops (74AC74) in cascade
configuration with the Q output of the first one being the input of the
second one. Then I "AND" the two Q's and I get the logic 1 I'm looking for.
[ASCII schem. snipped]

However, the room I have on the board is very scarce and I would like to
take advantage of the 4 schmitt trigger inverters I have in a 74AC14
chip. This chip is used along with 3 out of 4 AND gates in a 74AC08 to
create the above mentionned data line.

Just put the whole schmear in one little CPLD or FPGA or something.

Good Luck!
Rich

My favorite fix for situations like this is to make a "daughter board"
with pins that fit an existing "socket" pattern on the original board.

...Jim Thompson
 
J

Joerg

Jan 1, 1970
0
Hello Rich,
Just put the whole schmear in one little CPLD or FPGA or something.

And then watch the ammeter peg and the battery being slurped dry in no
time ;-)

Regards, Joerg
 
O

OBones

Jan 1, 1970
0
Rich said:
Just put the whole schmear in one little CPLD or FPGA or something.

I know I could do that, but the cost of getting a development system for
this cannot be justified. This is a "hobbyist" project, and I'd rather
make this with regular logic.
 
K

Keith Williams

Jan 1, 1970
0
Hello Rich,


And then watch the ammeter peg and the battery being slurped dry in no
time ;-)

The Xilinx CoolRunner II parts seem to be pretty low power, though I've not
used one.
 
J

Joerg

Jan 1, 1970
0
Hello Keith,
The Xilinx CoolRunner II parts seem to be pretty low power, though I've not
used one.

Yes, once in a while you see one that isn't a power hog. Like the old
Intel series. But usually they are. The other problem is that the cost
of the BOM would increase by one to two orders of magnitude in this case.

Regards, Joerg
 
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