Related to SPI interface ....

[KRK]

What is the maximum no. of devices connected to SPI? What is the maximum bus capacitance of SPI?

 

[Harald Kapp]

There is afaik no defined upper limit on the number of devices connected to an SPI bus.

The max. bus capacitance depends on the driver strength of the components used and the clock frequency.
The higher the clock frequency, the less time is available for charging or discharging the bus capacitance, therefore a smaller capacitance is allowed.
The higher the driver strength, the faster the bus capacitance is charged or discharged, therefore a higher bus cpacitance is allowed.
As far as I know these limits are not defined per standard. You'll have to look up the parameters in the datasheets of the components used.

 

[KRK]

When connecting the I2C/SPI for multiple devices we may route parallel the signals to multiple devices, will the parallel stub affects the data quality?

 

[Harald Kapp]

will the parallel stub affects the data quality?

Depending on your clock rate, rise times and fall times of the signal as well on the length of the stubs and the characteristic impedance: yes or no.
You'll have to apply transmission line theory or at least youÄll have to consider whether it is applicable with respect to the physical parameters of your circuit. At clock frequencies of a few kHz and slow rise/fall times there is usually no issue with refelxions and such.
At clock frequencies in the MHz range and fast signals, this becomes an issue and matched impedances are required to minimize detrimental effects. It may be better to use a bus going from device to device and attach each device with a short stub than to rout the SPI bus in parallel to different devices. In most cases this will save PCB real estate, too.