Re-inventing the wheel: quadrature decode - decode.gif (0/1)

[Robert Scott]

I needed to read a quadrature incremental encoder signal into a PIC
that has only counters, so I designed a decoder using D flip-flops and
some gates. I know this has been done to death, but I couldn't put my
finger on someone's previous design. So now I am wondering if my
design is anywhere near optimal. I know that it may not agree with
other designs in the case were the A-phase and the B-phase both change
within the same clock period, but I only care about the behavior when
the quadratue signals are slower than the HF-clock. The output of the
circuit is UP and DOWN count pulses that go to counters that I will
subtract in software. I hope the attachement (decode.gif) comes out
OK, so I don't have to render this schematic in ASCII graphics!


-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

 

[Frank Bemelman]

I needed to read a quadrature incremental encoder signal into a PIC
that has only counters, so I designed a decoder using D flip-flops and
some gates. I know this has been done to death, but I couldn't put my
finger on someone's previous design. So now I am wondering if my
design is anywhere near optimal. I know that it may not agree with
other designs in the case were the A-phase and the B-phase both change
within the same clock period, but I only care about the behavior when
the quadratue signals are slower than the HF-clock. The output of the
circuit is UP and DOWN count pulses that go to counters that I will
subtract in software. I hope the attachement (decode.gif) comes out
OK, so I don't have to render this schematic in ASCII graphics!

Attached files are automatically removed. Post your schematic
on a website or post in alt.binaries.schematics.electronic

Without having seen the schematic, I wonder if you really
need those FF's, you could perhaps do that in software too.

 

[Costas Vlachos]

Attached files are automatically removed. Post your schematic
on a website or post in alt.binaries.schematics.electronic

That's interesting - I also thought it wouldn't be possible to post binaries
here. But it is! At least my news server allows this. And I can read others'
binaries too...

Costas

 

[Robert Scott]

Attached files are automatically removed. Post your schematic
on a website..

Thanks for the suggestion. You can get the schematic image from

http://www.tunelab-world.com/decode.gif



-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

 

[Stefan Heinzmann]

That's interesting - I also thought it wouldn't be possible to post binaries
here. But it is! At least my news server allows this. And I can read others'
binaries too...

It seems that some newsreaders recognize uuencoded data and decode it
automatically. As uuencoded data is ASCII text, the news servers don't
remove it.

 

[Winfield Hill]

Robert Scott wrote...

http://www.tunelab-world.com/decode.gif

I would have expected a symmetry so the circuitry
associated with the two clock inputs would be the
same, did you mis-draft the circuit?

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Jim Thompson]

Thanks for the suggestion. You can get the schematic image from

http://www.tunelab-world.com/decode.gif



-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

Are you trying to make the classic rotary direction decoder?

...Jim Thompson

 

[Robert Scott]

Robert Scott wrote...

I would have expected a symmetry so the circuitry
associated with the two clock inputs would be the
same, did you mis-draft the circuit?

I don't think so. The two phase inputs are not symmetrical because
for up-counting, one particular phase leads the other. Can you find
an example where my circuit misbehaves?

-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

 

[Robert Scott]

Are you trying to make the classic rotary direction decoder?

Yes. Did I succeed?


-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

 

[Jim Thompson]

Thanks for the suggestion. You can get the schematic image from

http://www.tunelab-world.com/decode.gif



-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

See "ExternallyClockedQuadratureDecoder.pdf" on the S.E.D/Schematics
Page of my website.

There's also a version with self-clocking from the phase inputs, but I
can't seem to recall what I called it in my archives ;-)

...Jim Thompson

 

[Robert Scott]

See "ExternallyClockedQuadratureDecoder.pdf" on the S.E.D/Schematics
Page of my website.

It is neat, but I don't want to use a PROM, and what I really want is
comments on my circuit.


-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply address is fake.)

 

[Frank Bemelman]

It is neat, but I don't want to use a PROM, and what I really want is
comments on my circuit.

I would add some simple RC filters, to reduce noise, followed by
schmitt-trigger inputs perhaps. Or a HCTL2000 chip, if you can afford
the i/o pins.

 

[petrus bitbyter]

I needed to read a quadrature incremental encoder signal into a PIC
that has only counters, so I designed a decoder using D flip-flops and
some gates. I know this has been done to death, but I couldn't put my
finger on someone's previous design. So now I am wondering if my
design is anywhere near optimal. I know that it may not agree with
other designs in the case were the A-phase and the B-phase both change
within the same clock period, but I only care about the behavior when
the quadratue signals are slower than the HF-clock. The output of the
circuit is UP and DOWN count pulses that go to counters that I will
subtract in software. I hope the attachement (decode.gif) comes out
OK, so I don't have to render this schematic in ASCII graphics!


-Robert Scott
Ypsilanti, Michigan
(Reply through this forum, not by direct e-mail to me, as automatic reply

address is fake.)

Robert,

As far as my memory goes back this was ever presented to me a "classic"
problem with a "classic" solution. You needed only two edge-triggered
D-flipflops. One's data input was A and it was clocked by B, the others data
input was B and it was clocked by A. In your circuit you can add two
flipflops to synchronize with HF-clock. The only problem was that you had to
stop counting when both outputs had the same value. I neither analised nor
used it but it may give you some thoughts.

petrus