RAM simulation using Multisim

[evol_w10lv]

Hi!
The task is to simulate 8 rows (pins) 256 cells RAM using Multisim. I guess, it's 256x8 RAM, but Multisim gives just various versions of 8Kx8 Asyncronous Static RAM and 2KxRAM (in the picture):

Can I use it? Or there is specific soulution to simulate RAM?

 

[kpatz]

Depending on how you need to simulate it, just use the 2Kx8 RAM and only use the lower 8 address lines, tying the rest to ground.

Then you're just using 256x8 of the 2Kx8 RAM.

 

[evol_w10lv]

I tried something like this:

There was notification - "Placing a wire over a junction is not allowed." What's wrong there?
And what about schematics? Is it looks correct?
Also.. I guess, WE and OE must never both be active at the same time.. so I have to use other switch?

 

[kpatz]

When did you get the "Placing a wire over a junction is not allowed" message? When you were placing a wire? It should give you some indication where the issue is when it happens. I don't see any issues with your schematic as it is now.

The CS line can be tied low, there's no need for a switch on that line unless you need to disable the chip (usually to select which chip to access in circuits with multiple RAMs).

The truth table in the datasheet has no mention of what happens if both WE and OE are high. If they're mutually exclusive, you could use one switch and an inverter.

What are the I/O pins connected to?

You could use SPST switches along with pull-up or pull-down resistors as well.

 

[evol_w10lv]

It's OK now with that warning message. And it's clear about CS line, but now I have got other misunderstanding:

What are the I/O pins connected to?

I was wrong there with probes. Actually, I want to see results of simulation, when I'm simulating "write" and "read" operation. It means, I have to somehow use buffer memory there, which has to be connected to these I/O pins?

 

[kpatz]

I'm not familiar with how Multisim works, so you're on your own there.

In any case, you'll need to set things up to place data bits on the I/O lines for writes and to "get" the bits from the RAM for reads.

A few 74HC125 tri-state buffer ICs, and a logic gate or two will enable you to create a circuit to "separate" the input and output of the I/O lines. Then you can feed a DIP switch into the inputs for writing, and monitor the outputs when reading.

If you need the last-read byte to remain available on the outputs while writing another byte to the RAM, add a 74LS373 octal transparent latch.

 

[evol_w10lv]

Nice idea about buffer ICs.
I made some corrections:

And here is an example:

Is it looks good enough for you?

When OE (Read) is ON, I can see ligths on. When OE is OFF, lights are off, as it should be. But using this simulaton, I can write data even then, when WE (Write) is OFF. I guess, it's not correct. Or is it acceptable? And S1 and S4 DIP swithces must be in the same state, so key numbers are the same for both switces?

As I'm an amatuer and still studying this theme, I want to be sure, that I understand it correctly. Maybe you can explain it, answering to my question?
I/O output pins are for storage or extracted for data reading. And in real life these pins are connected with CPU or extra memory?

 

[kpatz]

Looks good to me, except for one thing: TTL (74LS parts) default to logic high if floating, so DIP switches to 5V won't pull the buffer inputs low when off. Either tie that DIP switch to ground and have switch-on be logic low, or use a 74HC241 and add pull-down resistors.

OE is output enable, so that enables reading. WE overrides OE so that's why you can write with WE low regardless of OE's state. When WE is low, the outputs become inputs so OE becomes irrelevant.

I'm not familiar with Multisim, but if you find the two sets of DIP switches are locked together there's probably some sort of key or ID value that is the same for both, and changing one of them will fix it. Did you copy & paste one DIP switch to create the other? Try selecting it from the component list (or whatever method is used to add components in Multisim) instead.

In real life the I/O pins would be connected to a CPU's data bus, and the address pins to the CPU's address bus (with additional logic to split the addresses into banks for ROM, RAM, memory-mapped I/O devices, etc). The OE and WE pins would go to corresponding pins on the CPU (possibly with additional logic for device selection), and the CPU handles reads and writes automatically. The CS pin would typically be tied to the address logic so that the RAM is selected when the appropriate address range is requested by the CPU.

Generally RAMs aren't hooked up to DIP switches like your circuit, but it can be done for the purpose of learning how the RAM works without the additional complexity of understanding how the CPU works.

Another tip to simplify your circuit: instead of having separate "read" and "write" DIP switches, use a single switch and an inverter to set OE and WE to opposite states (OE=high, WE=low for one switch position and OE=low, WE=high for the other), and tie the tristate pins on the buffer to the corresponding RAM pin. Then you can simply flip the switch one way to read, and the other way to write.

 

[evol_w10lv]

I guess, it will be good enough without simplifying these switches.

The truth table in the datasheet has no mention of what happens if both WE and OE are high. If they're mutually exclusive, you could use one switch and an inverter.

Speaking about datasheet, you were using this one http://www.alldatasheet.com/datasheet-pdf/pdf/77359/HITACHI/HM6116.html? for data? Multisim says that it's 2Kx8 RAM 200nS. So.. this is access time? But I don't understand about it. That time access is a kind of "speed"? But I'm jusing 256x8, it don't change anything in the time access, because it's just a part of whole RAM?

Also I add pull-down resistors:

And in our case, tri-state buffer is used only to see output of signal/data and there is no conection with real life. Something like DIP switch is used to give data for RAM, but in real life, CPU gives and read data from RAM. Am I correct?

 

[kpatz]

Access time is the average speed that the RAM responds to inputs. There are timing waveforms in the datasheet showing this in detail. It's largely a function of the chip's design, in terms of propagation delay and gate-charge times. There's no difference in access speed whether you're using 1 byte, 256 bytes or all 2K. It's called "random access" because you can access any byte of the RAM in the same amount of time.

Your last paragraph is correct too. RAM is used as dynamic program and data storage for microprocessors (CPUs), since they have very little storage built-in. The RAM in your computer is basically the same thing, except that computers usually use dynamic rather than static RAM. Dynamic RAM uses microscopic capacitors to store bits instead of flip-flops, which allows for more capacity per chip, but they require a circuit to "refresh" the bits since the capacitors discharge over time. Static RAM can hold data indefinitely for as long as the chip receives power, no "refreshing" is required.

Microcontrollers have more built-in storage than microprocessors, but those are just RAM and ROM included on-chip. These are usually much smaller than standalone RAM/ROM chips.

 

[evol_w10lv]

Thanks for helping.
At least I'm back.. unfortunately I have got one misunderstanding again.
We know that data writes into array like this:

Of course in my simulation not array, there I can just understand write and read options/functions, so I use just column address.
But what about row address.. I add preview:

Here I write data in, for example, in three column addresses, but how "RAM knows" in which row address data have to be stored?

 

[kpatz]

Long story short, the address you give the RAM is a combination of row and column.

The address you provide to the RAM is a certain number of bits depending on the size of the RAM. For a 2K RAM, it's 11 bits. For a 256 byte RAM, it's 8 bits. These bits are divided up to make the row and column addresses. For simplicity's sake, we'll look at a 256 byte RAM. It has 8 address bits, which are divided into 2 4-bit addresses, one for row and one for column. There would be 16 rows x 16 columns, so the upper 4 bits would address the row and the lower 4 bits the column (or vice versa).

Larger RAMs may even go beyond rows and columns, into banks. So, instead of a single matrix, there would be 2 or more. For example, a 64K RAM may be made of 4 16K banks that have 128 rows and 128 columns each. 7 bits of the address would be the row address, 7 bits the column, and 2 bits to select the bank for a total of 16 address bits.

The arrays don't have to be square either. A 32K chip could use a 256 row x 128 column array, for example. In this case there would be a different number of bits in the column and row addresses.

So, in short, physically the RAM is made up of rows, columns and banks, but from an end-user perspective this doesn't matter. You can look at a 256 byte RAM as being a 256x1 array, a 128x2, etc. It all depends on how you interpret the address bits.

Then to add another wrinkle, any RAM that carries more than 1 bit (such as your 2Kx8) actually has a bank of RAM for each bit. They're addressed in parallel to give you the 8 bits. So, if you were to examine your chip under a microscope, you may see 8 separate arrays, or 8 groups of arrays. Many computers use 1-bit RAM, so to get bytes you needed to install 8 chips (back in the day of using DIP package RAM). The DIMMs you see in modern computers has a chip for each bit, which is why there's usually 8 or 16 chips on a DIMM.

 

[evol_w10lv]

At least I start to understand it..
For example, without any simulation, maybe to explain RAM'S work in my homework, I can use something like that:

Then if there will be CPU or microcontroller, BUS1 to microcontroller's input, microcontroller's output to BUS2, BUS2 to RAM's input, RAM'S output to BUS1, RAM's OE and WE to microcontroller... or something like that.
If it looks acceptable for you, then I could use this schematics also. What's your opinion?

 

[kpatz]

Someone might ask why you're not using A8-A10. If it's just a conceptual circuit drawing for homework, why not have all 11 bits of the address on BUS2? Is there a requirement that you only use 256 bytes of RAM? Might as well let the microcontroller use all of it.

Other than that it looks good.

 

[evol_w10lv]

Thank for your help again. Now all should be clear.
And yes, it's like a project. The task is to simulate even 256x8 RAM and discribe it.

 

[Ken Lawrence]

How do I upload the files?