Question re booting a 68000 CPU

[jamma-plusser]

What are the essential signals required by a 68000 CPU in order to get
its address lines active?

Obviously Clock and Reset - but what else MUST be functional?

I ask as I repair arcade PCBs and usually concentrate on 6502, 8080
and Z80 boards. However I've recently starting fixing up a few
68000-based boards from the late 80s/early 90s and a few, despite
having valid Clock and Reset signals, are doing absolutely bugger all,
ie no activity on any address lines, etc.

Now a 6502, 8080 or Z80 will fire up the address lines if they have
valid Clock and Reset signals, but apparently this isn't the case with
the 68000. Or is it? Does it also need to grab a valid piece of boot
code from a connected ROM or EPROM?

Ta!

 

[Charmed Snark]

jamma-plusser expounded in

What are the essential signals required by a 68000 CPU in order to get
its address lines active?

Obviously Clock and Reset - but what else MUST be functional?

I ask as I repair arcade PCBs and usually concentrate on 6502, 8080
and Z80 boards. However I've recently starting fixing up a few
68000-based boards from the late 80s/early 90s and a few, despite
having valid Clock and Reset signals, are doing absolutely bugger all,
ie no activity on any address lines, etc.

Your phasers are defective.

Snark.

 

[IanM]

What are the essential signals required by a 68000 CPU in order to get
its address lines active?

Obviously Clock and Reset - but what else MUST be functional?

I ask as I repair arcade PCBs and usually concentrate on 6502, 8080
and Z80 boards. However I've recently starting fixing up a few
68000-based boards from the late 80s/early 90s and a few, despite
having valid Clock and Reset signals, are doing absolutely bugger all,
ie no activity on any address lines, etc.

Now a 6502, 8080 or Z80 will fire up the address lines if they have
valid Clock and Reset signals, but apparently this isn't the case with
the 68000. Or is it? Does it also need to grab a valid piece of boot
code from a connected ROM or EPROM?

Ta!

If you dont get a better reply in a day or so, I'll dig out my 68000
documetation and look it up for you but IIRC all memory accesses not in
6800 compatibility mode needed a handshake. The address decoder must
assert /DTACK for each memory cycle. 6800 compatibility was obtained by
asserting /VPA at the start of the access cycle. The vector table is
initialised from ROM when the CPU comes out of reset. The NOP
instruction is *not* all zeros, but if you stuff the bus with zeros, it
should accept the vector table and execute OR instruuctions with one of
the registers till the cows come home.

 

[jamma-plusser]

If you dont get a better reply in a day or so, I'll dig out my 68000
documetation and look it up for you but IIRC all memory accesses not in
6800 compatibility mode needed a handshake. The address decoder must
assert /DTACK for each memory cycle. 6800 compatibility was obtained by
asserting /VPA at the start of the access cycle. The vector table is
initialised from ROM when the CPU comes out of reset. The NOP
instruction is *not* all zeros, but if you stuff the bus with zeros, it
should accept the vector table and execute OR instruuctions with one of
the registers till the cows come home.

Thanks, appreciate the info.

 

[Quiki]

Hi,
I believe the 68000 is picky about it's /HLT line being released in concert with its /RST line upon first starting up. /HLT is pin 17, /RST is 18 on the DIP-64. Also, while being clocked, the chip requires at least 100ms with /HLT and /RST asserted (low).

Better late than never in this response. Maybe it'll help the next guy.