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PSpice: Simulation of differential ECL gates

Hi.

I currently simulate digital ECL circuits using ideal parts from
"dig_prim.olb". I put a DELAY on each gate's output to simulate the
propagation delay. This is important because the propagation delays
are in the dimension of a clock cycle.

Is anyone out there who also uses PSpice to simulate ECL circuits?
Does anyone know a more appropriate way therefor? Fore example the
availability of true ECL models?


Regards,
Norbert
 
C

Charlie E.

Jan 1, 1970
0
Hi.

I currently simulate digital ECL circuits using ideal parts from
"dig_prim.olb". I put a DELAY on each gate's output to simulate the
propagation delay. This is important because the propagation delays
are in the dimension of a clock cycle.

Is anyone out there who also uses PSpice to simulate ECL circuits?
Does anyone know a more appropriate way therefor? Fore example the
availability of true ECL models?


Regards,
Norbert

Last time I looked there was an ECL library, so, yes, there are true
ECL libraries available. I never did that much simulation with them
though, although they are included in the digio.lib, and they took
great pains (and it was painful!) to make the levels come out right.

Charlie
Edmondson Engineering Inc.
 
Some of us have our own personalized 10K, 100K plus ECLIPS ;-)

Do you mean ECLinPS? I cannot find (P)Spice models for ECLinPS.
 
I rolled my own, but I'm in the chip design business ;-)

How complete is your "own" ECLinPS library?

Could you send me a copy of it?
 
C

Charlie E.

Jan 1, 1970
0
PSpice does not support IBIS models.

...Jim Thompson

Also, remember, IBIS is purely an I/O model, not any type of form or
functionaliity, including internal delays and timing. they are
designed for signal integrity purposes, only.

Charlie
 
K

krw

Jan 1, 1970
0
To-Email- said:
Yep. In other words, totally useless for anything other than PCB
track analysis.

They're useful in designing the opposite end, as well. IOW,
"purely I/O models". ;-)
 
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