pspice changing time step issue

[panfilero]

I have a couple issues I'm having trouble with, I'm using orcad 16 and
trying to simulate a simple circuit, it's basically two pulse
generators VPULSE each going through a diode... I'm trying to "diode-
or" two voltage sources... but I keep getting these large voltage
spikes.... say if I set the pulses at 12V I get these 16V spikes...
and then they settle to 12V here is my circuit, where V1 and V2 are 12
Volt pulses slightly offset from one another... I was especting to
seee 12 V on the Vout regardless of whether V1, V2 or both were on


V1 O-----|>|-------
D1 |
|-------------O Vout
|
V2 O-----|>|-------
D2


My other issue is, I try to set my pulses for 1 second each and then
want my simulation to go to 3 seconds, but it takes forever to run
through the simulation, does anyone know how I can speed that up....
can I change the sampling rate or something so it would fnish faster?

Much thanks
J.

 

[MooseFET]

I have a couple issues I'm having trouble with, I'm using orcad 16 and
trying to simulate a simple circuit, it's basically two pulse
generators VPULSE each going through a diode... I'm trying to "diode-
or" two voltage sources... but I keep getting these large voltage
spikes.... say if I set the pulses at 12V I get these 16V spikes...
and then they settle to 12V here is my circuit, where V1 and V2 are 12
Volt pulses slightly offset from one another... I was especting to
seee 12 V on the Vout regardless of whether V1, V2 or both were on

V1 O-----|>|-------
D1 |
|-------------O Vout
|
V2 O-----|>|-------
D2

My other issue is, I try to set my pulses for 1 second each and then
want my simulation to go to 3 seconds, but it takes forever to run
through the simulation, does anyone know how I can speed that up....
can I change the sampling rate or something so it would fnish faster?

Do you have a load resistor on the circuit or is the two diodes the
whole thing?

Spice sometimes gives wild results for circuits that won't work. With
no load resistor, the Vout node is basically floating when the two
diodes are off.

 

[panfilero]

Do you have a load resistor on the circuit or is the two diodes the
whole thing?

Spice sometimes gives wild results for circuits that won't work.  With
no load resistor, the Vout node is basically floating when the two
diodes are off.- Hide quoted text -

- Show quoted text -

I do have a load resistor.... and also grounds, would you expect a
voltage spike in a circuit like this?

 

[Wimpie]

I have a couple issues I'm having trouble with, I'm using orcad 16 and
trying to simulate a simple circuit, it's basically two pulse
generators VPULSE each going through a diode... I'm trying to "diode-
or" two voltage sources... but I keep getting these large voltage
spikes.... say if I set the pulses at 12V I get these 16V spikes...
and then they settle to 12V here is my circuit, where V1 and V2 are 12
Volt pulses slightly offset from one another... I was especting to
seee 12 V on the Vout regardless of whether V1, V2 or both were on

V1 O-----|>|-------
D1 |
|-------------O Vout
|
V2 O-----|>|-------
D2

My other issue is, I try to set my pulses for 1 second each and then
want my simulation to go to 3 seconds, but it takes forever to run
through the simulation, does anyone know how I can speed that up....
can I change the sampling rate or something so it would fnish faster?

Much thanks
J.

Hello,

You might reduce the minimum conductance (GMIN). Depending on the load
resistance you can reduce it significantly. Also check your maximum
step size. As this is 1us, it takes 3e6 steps to run the simulation.

Regarding the spikes. When you have a pulse source with 1us rise and
fall times, you may reduce the maximum step size to below 1us (but
this will cause long sim times when you run for 3s). Other option is
increase the rise and fall times of your pulse sources and increase
the step size also, this will speed up your simulation.

What type of diode do you use? Try another one (for example a 1n4148)
and see what happens). Keep in mind that real diodes have capacitance.
When the output is already 12V, you can get a spike via the diode that
has been connected to the source that goes from low to high. So it may
not be a simulation error.

When I have doubts about a circuit, I play with the max step size
setting.

Best regards,

Wim
PA3DJS
www.tetech.nl

remove abc from the mail address.

 

[panfilero]

Hello,

You might reduce the minimum conductance (GMIN). Depending on the load
resistance you can reduce it significantly.  Also check your maximum
step size. As this is 1us, it takes 3e6 steps to run the simulation.

Regarding the spikes. When you have a pulse source with 1us rise and
fall times, you may reduce the maximum step size to below 1us (but
this will cause long sim times when you run for 3s). Other option is
increase the rise and fall times of your pulse sources and increase
the step size also, this will speed up your simulation.

What type of diode do you use? Try another one (for example a 1n4148)
and see what happens). Keep in mind that real diodes have capacitance.
When the output is already 12V, you can get a spike via the diode that
has been connected to the source that goes from low to high. So it may
not be a simulation error.

When I have doubts about  a circuit, I play with the max step size
setting.

Best regards,

Wim
PA3DJSwww.tetech.nl

remove abc from the mail address.- Hide quoted text -

- Show quoted text -

I keep getting errors like this now:

"ERROR -- Convergence problem in transient analysis at Time = .133
Time step = 72.00E-21, minimum allowable step size =
1.000E-18

These voltages failed to converge:

V(N902046) = 5.041uV \ 2.644uV

These supply currents failed to converge:

I(V_V1) = 2.343mA \ -5.677uA
I(V_V2) = 2.354mA \ 4.846uA

These devices failed to converge:
X_D1.D1 "


How do I change the step size? I see maximum step size option, but no
minimum... wouldn't I want to change the minimum step size to make the
simulation run faster? Do you know what these errors mean?
Thanks

 

[Helmut Sennewald]

I have a couple issues I'm having trouble with, I'm using orcad 16 and
trying to simulate a simple circuit, it's basically two pulse
generators VPULSE each going through a diode... I'm trying to "diode-
or" two voltage sources... but I keep getting these large voltage
spikes.... say if I set the pulses at 12V I get these 16V spikes...
and then they settle to 12V here is my circuit, where V1 and V2 are 12
Volt pulses slightly offset from one another... I was especting to
seee 12 V on the Vout regardless of whether V1, V2 or both were on


V1 O-----|>|-------
D1 |
|-------------O Vout
|
V2 O-----|>|-------
D2


My other issue is, I try to set my pulses for 1 second each and then
want my simulation to go to 3 seconds, but it takes forever to run
through the simulation, does anyone know how I can speed that up....
can I change the sampling rate or something so it would fnish faster?

Much thanks
J.

Hello panfilero,

Please show your SPICE netlist, if you are interested in a helpful answer.
It's the .net and the .cir file.

Best regards,
Helmut

 

[panfilero]

Hello panfilero,

Please show your SPICE netlist, if you are interested in a helpful answer.
It's the .net and the .cir file.

Best regards,
Helmut- Hide quoted text -

- Show quoted text -

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1 N899662 N901787 D120NQ045
X_D2 N900764 N901787 D120NQ045
V_V1 N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2 N900764 0
+PULSE 12 12 0 1p 1p 1 2





** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 3 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
.INC "..\SCHEMATIC1.net"


.END

 

[Helmut Sennewald]

Newsbeitrag








Hello panfilero,

Please show your SPICE netlist, if you are interested in a helpful answer.
It's the .net and the .cir file.

Best regards,
Helmut- Hide quoted text -

- Show quoted text -

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1 N899662 N901787 D120NQ045
X_D2 N900764 N901787 D120NQ045
V_V1 N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2 N900764 0
+PULSE 12 12 0 1p 1p 1 2


Hello,

I have looked at your circuit and simulated it with LTspice.

It's quite normal to see the large voltage spike
at the output, because your diodes have a few nano-Farads
capacitance and you drive it extremely "hard" with
your voltage sources (Trise=1ns, Ri=0Ohm).
The junctiom capacitance is the reason for the
voltage spikes. (SPICE model: CJO=11.509E-9)
If you add a capacitor to the output, the spikes
will become very small.


Best regards,
Helmut




** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
..lib "nom.lib"

*Analysis directives:
..TRAN 0 3 0
..PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
..INC "..\SCHEMATIC1.net"


..END

 

[panfilero]

Newsbeitragnews:67d261ba-2ce3-49fd-9447-fb4c83f9395a@s12g2000prg.googlegroups.com...

Hello panfilero,

Please show your SPICE netlist, if you are interested in a helpful answer.
It's the .net and the .cir file.

Best regards,
Helmut- Hide quoted text -

- Show quoted text -

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1         N899662 N901787 D120NQ045
X_D2         N900764 N901787 D120NQ045
V_V1         N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2         N900764 0
+PULSE 12 12 0 1p 1p 1 2

Hello,

I have looked at your circuit and simulated it with LTspice.

It's quite normal to see the large voltage spike
at the output, because your diodes have a few nano-Farads
capacitance and you drive it extremely "hard" with
your voltage sources (Trise=1ns, Ri=0Ohm).
The junctiom capacitance is the reason for the
voltage spikes. (SPICE model: CJO=11.509E-9)
If you add a capacitor to the output, the spikes
will become very small.

Best regards,
Helmut

** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN  0 3 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
.INC "..\SCHEMATIC1.net"

.END- Hide quoted text -

- Show quoted text -

I"ll try that, I really appreciate the help! Thanks

 

[MooseFET]

I do have a load resistor.... and also grounds, would you expect a
voltage spike in a circuit like this?

No I wouldn't.

What sort of diodes is it and what sort of spice?

 

[MooseFET]

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1 N899662 N901787 D120NQ045
X_D2 N900764 N901787 D120NQ045
V_V1 N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2 N900764 0
+PULSE 12 12 0 1p 1p 1 2

Hello,

I have looked at your circuit and simulated it with LTspice.

It's quite normal to see the large voltage spike
at the output, because your diodes have a few nano-Farads

Clarification:
if 12V=Large the above is correct
if 1000V= large this isn't what you were seeing

Most likely you saw 12V spikes.

capacitance and you drive it extremely "hard" with
your voltage sources (Trise=1ns, Ri=0Ohm).
The junctiom capacitance is the reason for the
voltage spikes. (SPICE model: CJO=11.509E-9)
If you add a capacitor to the output, the spikes
will become very small.

Best regards,
Helmut

** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 3 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
.INC "..\SCHEMATIC1.net"

.END

 

[Helmut Sennewald]

Clarification:
if 12V=Large the above is correct
if 1000V= large this isn't what you were seeing

Most likely you saw 12V spikes.

Hello

We talked about a spike with 4V on top of the 12V DC.

Best regards,
Helmut


PS: The rectifier has two 120A diodes 120NQ045.
http://www.datasheetcatalog.com/datasheets_pdf/1/2/0/N/120NQ045.shtml

 

[[email protected]]

Hello panfilero,

Please show your SPICE netlist, if you are interested in a helpful answer.
It's the .net and the .cir file.

Best regards,
Helmut- Hide quoted text -

- Show quoted text -

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1 N899662 N901787 D120NQ045
X_D2 N900764 N901787 D120NQ045
V_V1 N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2 N900764 0
+PULSE 12 12 0 1p 1p 1 2

** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 3 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
.INC "..\SCHEMATIC1.net"

.END

Hello,

When I look into your circuit, it seems a little bit unpractical:

You are using power diodes in combination with ps pulses. You might
reduce the rise and fall times of your sources and add a load resistor
(to ground for example). When the load resistance is not in the many
Meg Ohms, you might reduce the GMIN parameter (it will probably
default in the 1e-12 range).

This may help to converge the simulation process. Pspice reduces its
time step until the specified accuracy is reached (with a certain
minimum time step). When the iterative process does not converge, you
get the minimum time step error.

Probably you will add inductances in the future. Inductances in
combination with diodes are the key ingredients for convergence
problems. Using realistic components by adding loss resistances and
capacitances to inductors, helps to speed up your simulations.

Hope this helps a bit.

Best regards,

Wim
PA3DJS
www.tetech.nl
remove abc from the mail address.

 

[[email protected]]

On Mar 14, 3:00 pm, "Helmut Sennewald" <[email protected]>
wrote:

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1 N899662 N901787 D120NQ045
X_D2 N900764 N901787 D120NQ045
V_V1 N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2 N900764 0
+PULSE 12 12 0 1p 1p 1 2

** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 3 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
.INC "..\SCHEMATIC1.net"

.END

Hello,

When I look into your circuit, it seems a little bit unpractical:

You are using power diodes in combination with ps pulses. You might
reduce the rise and fall times of your sources and add a load resistor
(to ground for example). When the load resistance is not in the many
Meg Ohms, you might reduce the GMIN parameter (it will probably
default in the 1e-12 range).

Small error, you should increase it (for example from 1e-12 to
1e-9).

This may help to converge the simulation process. Pspice reduces its
time step until the specified accuracy is reached (with a certain
minimum time step). When the iterative process does not converge, you
get the minimum time step error.

Probably you will add inductances in the future. Inductances in
combination with diodes are the key ingredients for convergence
problems. Using realistic components by adding loss resistances and
capacitances to inductors, helps to speed up your simulations.

Hope this helps a bit.

Best regards,

Wim
PA3DJSwww.tetech.nl
remove abc from the mail address.

best regards,

Wim

 

[JosephKK]

Hello panfilero,

Please show your SPICE netlist, if you are interested in a helpful answer.
It's the .net and the .cir file.

Best regards,
Helmut- Hide quoted text -

- Show quoted text -

Hi Helmut,

Here's my netlist and .cir files... thanks for taking a look at this

* source Test_
X_D1 N899662 N901787 D120NQ045
X_D2 N900764 N901787 D120NQ045
V_V1 N899662 0
+PULSE 12 0 15u 1n 1n 1 2
V_V2 N900764 0
+PULSE 12 12 0 1p 1p 1 2





** Creating circuit file "Test_.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY
SUBSEQUENT SIMULATIONS

*Libraries:
* Profile Libraries :
* Local Libraries :
* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_16.0\tools\PSpice
\PSpice.ini file:
.lib "nom.lib"

*Analysis directives:
.TRAN 0 3 0
.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*))
NOISE(alias(*))
.INC "..\SCHEMATIC1.net"


.END

I see no load device. What is up with the picosecond edges on V_V2?