PIC for clock divider?

[Matt Clement]

I was told to research if a PIC clock divider would be better or worse than
using a CPLD divider. I would think that a combinatorial logic would be
more reliable than some software running on a PIC?? Also the jitter would
be less with propogation delay on discrete logic than a PIC??

We are looking to create a 10Khz clock from something much faster. It needs
to be a stable/clean output.
Anyone have any comments or things I could research?

thanks

 

[M.Randelzhofer]

I was told to research if a PIC clock divider would be better or worse than
using a CPLD divider. I would think that a combinatorial logic would be
more reliable than some software running on a PIC?? Also the jitter would
be less with propogation delay on discrete logic than a PIC??

We are looking to create a 10Khz clock from something much faster. It needs
to be a stable/clean output.
Anyone have any comments or things I could research?

thanks

A uC timer can be used as an integer clock divider for moderate frequencies
(up to 10 or more MHz), and thats reliable and without jitter, if programmed
correctly.
The main advantage is, that you can use the processor core for additional
purposes, and an available BOR (Brown Out Reset) for the whole system.
The clock to output time of the uC may be a problem, if not defined in the
data sheet.

A CPLD or FPGA divider can be much faster, with a defined tco, some FPGA's
allow zero tco with internal PLL's or DLL's.

Your selection also depends what you can do with the rest of the resources
of the CPLD/FPGA or uC.

MIKE

--
www.oho-elektronik.de
OHO-Elektronik
Michael Randelzhofer
FPGA und CPLD Mini Module
Klein aber oho !