Monostable made from OR gate and CR network , pulse duration ??

[Graham]

Discreet component monostabe constructed from a ‘TTL’ OR gate ,
resistor and capacitor , Im trying to determine what the pulse width
should be from the timing components, but I don’t see any info on this
configuration. I need to certify the cct is in specification .. Its
fed with a 0 > 5v step

From a common start point, one line direct to gate (1) input, from
the same common start point, a 220 ohm resistor connected to the
second gate (2) input.

From the junction of the 220 ohm resistor and the second gate input is
connected a 0.0022nF capacitor to ground.

The resistor and capacitor form a cr timing network.

Operation appears to be , the initial 'ON' voltage (5v) is applied
direct to gate (1) , the capacitor to ground delays the voltage
applied to gate (2) charging via the 220 resistor.

When the two inputs are at logic ‘1’ then the ‘OR’ Fnction changes the
gate state .

Im seeing a 650nS pulse , has anyone a formula or a chart that gives
a guide to pulse duration ?

 

[Franc Zabkar]

Discreet component monostabe constructed from a ‘TTL’ OR gate ,
resistor and capacitor , Im trying to determine what the pulse width
should be from the timing components, but I don’t see any info on this
configuration. I need to certify the cct is in specification .. Its
fed with a 0 > 5v step

From a common start point, one line direct to gate (1) input, from
the same common start point, a 220 ohm resistor connected to the
second gate (2) input.

From the junction of the 220 ohm resistor and the second gate input is
connected a 0.0022nF capacitor to ground.

The resistor and capacitor form a cr timing network.

Operation appears to be , the initial 'ON' voltage (5v) is applied
direct to gate (1) , the capacitor to ground delays the voltage
applied to gate (2) charging via the 220 resistor.

When the two inputs are at logic ‘1’ then the ‘OR’ Fnction changes the
gate state .

Im seeing a 650nS pulse , has anyone a formula or a chart that gives
a guide to pulse duration ?

An OR gate will have an output of 1 whenever input #1 is a logic 1,
regardless of what happens on input #2. OTOH, an XOR gate (eg 74LS86)
will behave as you describe.

A Motorola SN74LS86 has a guaranteed minimum input high voltage of
2.0V. This means that the output is guaranteed to change state when
the capacitor charges up to 2.0V. However, it may also change state at
1.5V, so trying to compute a pulse width would be difficult. All you
can calculate with any reasonable certainty is the *maximum* pulse
width, although this figure would also be affected by the current draw
into or out of the gate.

If we calculate the RC time constant, then ...

R x C = 220 x 0.0022 nF
= 0.484 ns

.... which is 1000x lower than you have measured.

Are you sure you didn't mean C = 0.0022uF ? This would result in an RC
value of 484ns.

The formula for the charging voltage, V, would be ...

-t/RC
V = Vo (1 - e )

.... where Vo = 5V.

The trigger point would be when V = 2.0V

This reduces to ...

t = -RC ln(1 - V/Vo)
= 247ns

- Franc Zabkar

 

[Arfa Daily]

An OR gate will have an output of 1 whenever input #1 is a logic 1,
regardless of what happens on input #2. OTOH, an XOR gate (eg 74LS86)
will behave as you describe.

A Motorola SN74LS86 has a guaranteed minimum input high voltage of
2.0V. This means that the output is guaranteed to change state when
the capacitor charges up to 2.0V. However, it may also change state at
1.5V, so trying to compute a pulse width would be difficult. All you
can calculate with any reasonable certainty is the *maximum* pulse
width, although this figure would also be affected by the current draw
into or out of the gate.

If we calculate the RC time constant, then ...

R x C = 220 x 0.0022 nF
= 0.484 ns

... which is 1000x lower than you have measured.

Are you sure you didn't mean C = 0.0022uF ? This would result in an RC
value of 484ns.

The formula for the charging voltage, V, would be ...

-t/RC
V = Vo (1 - e )

... where Vo = 5V.

The trigger point would be when V = 2.0V

This reduces to ...

t = -RC ln(1 - V/Vo)
= 247ns

- Franc Zabkar

Just a suggestion, but wouldn't it be a whole hell of a lot simpler to just
use a 555 timer IC ? Just the chip, two Rs and one C (two Cs if you want to
be pedantic and decouple the control pin) to make a monostable which will
give utterly predictable results over a wide supply voltage and temperature
range, and has a very simple timing formula of approx 0.7CR.

Arfa

 

[Franc Zabkar]

Just a suggestion, but wouldn't it be a whole hell of a lot simpler to just
use a 555 timer IC ? Just the chip, two Rs and one C (two Cs if you want to
be pedantic and decouple the control pin) to make a monostable which will
give utterly predictable results over a wide supply voltage and temperature
range, and has a very simple timing formula of approx 0.7CR.

Arfa

Another option would be a 74LS123. Perhaps the OP's application
doesn't require precision, and perhaps he has a spare gate.

- Franc Zabkar

 

[Arfa Daily]

Another option would be a 74LS123. Perhaps the OP's application
doesn't require precision, and perhaps he has a spare gate.

- Franc Zabkar

Granted. But as you say, the actual thresholds on TTL can vary widely from
family to family, which may give a huge discrepancy betwen the figure you
think you should get, and what you really do get. OK I suppose if it's just
something for yourself, but could cause problems if you were going to do a
few of them.

I was thinking also, that the circuit the OP is describing is in fact just a
(power on ??) delay with a buffer gate on the end, as there doesn't seem to
be any mechanism to reset the timing network after the initial pulse. Unless
of course, the OP's "common starting point" is in fact switched between rail
and ground. You sometimes used to see tricks like this on older logic
boards, to provide a delayed reset to other bits of circuitry such as a CPU
IC. These days, they tend to use dedicated reset ICs, which again, give
predictable and repeatable results.

Arfa

 

[Franc Zabkar]

Granted. But as you say, the actual thresholds on TTL can vary widely from
family to family, which may give a huge discrepancy betwen the figure you
think you should get, and what you really do get. OK I suppose if it's just
something for yourself, but could cause problems if you were going to do a
few of them.

I was thinking also, that the circuit the OP is describing is in fact just a
(power on ??) delay with a buffer gate on the end, as there doesn't seem to
be any mechanism to reset the timing network after the initial pulse. Unless
of course, the OP's "common starting point" is in fact switched between rail
and ground. You sometimes used to see tricks like this on older logic
boards, to provide a delayed reset to other bits of circuitry such as a CPU
IC. These days, they tend to use dedicated reset ICs, which again, give
predictable and repeatable results.

Arfa

Wouldn't a power-on reset pulse of less than 1us be much too short?

For example, Micrel's MIC2774 Dual Micro-Power Low Voltage Supervisor
"generates a 140ms (minimum) power-on reset pulse".

- Franc Zabkar

 

[Arfa Daily]

Wouldn't a power-on reset pulse of less than 1us be much too short?

For example, Micrel's MIC2774 Dual Micro-Power Low Voltage Supervisor
"generates a 140ms (minimum) power-on reset pulse".

- Franc Zabkar

Yes Franc, I think it would. But then the value of the OP's cap at 0.0022nF
seems unrealistically low, as well. I was thinking more in terms of 10k by
0.1uF when likening this to the old reset circuits ...

Arfa

 

[Graham]

Granted. But as you say, the actual thresholds on TTL can vary widely from
family to family, which may give a huge discrepancy betwen the figure you
think you should get, and what you really do get. OK I suppose if it's just
something for yourself, but could cause problems if you were going to do a
few of them.

I was thinking also, that the circuit the OP is describing is in fact just a
(power on ??) delay with a buffer gate on the end, as there doesn't seem to
be any mechanism to reset the timing network after the initial pulse. Unless
of course, the OP's "common starting point" is in fact switched between rail
and ground. You sometimes used to see tricks like this on older logic
boards, to provide a delayed reset to other bits of circuitry such as a CPU
IC. These days, they tend to use dedicated reset ICs, which again, give
predictable and repeatable results.

Arfa- Hide quoted text -

- Show quoted text -

Ok ... Well this birds nest is about 35 years old , your right on the
'tricks' bit , there is more than one set of discreat 'cr's' on the
board ,

I did the same calculation , with the long 'cr' time the vlaues given
may be attached to the device thats making a 0.125 uS pulse (measured
on teck-t 500 mhz dig scope)

CR = approx 62% full charge voltage, (5 volts) so i assume the devices
are toggeling at the zero to logic 1 transission voltage of the
chip ...which is less than 50% rail .... so its going over early ...

Ive not seen any guide lines on expected pulse duration from this
arrangement , 125 nano seconds is quite sharp even for the new
devices .... looks like , may be the only way is to remove the C ,
R , components , measure them and if in tolerance then assume that
what is measured is correct .... I could look at the charging curve
to see when it chnages state .. and work backwards ?

tnx - G ..

 

[Franc Zabkar]

Ok ... Well this birds nest is about 35 years old , your right on the
'tricks' bit , there is more than one set of discreat 'cr's' on the
board ,

I did the same calculation , with the long 'cr' time the vlaues given
may be attached to the device thats making a 0.125 uS pulse (measured
on teck-t 500 mhz dig scope)

CR = approx 62% full charge voltage, (5 volts) so i assume the devices
are toggeling at the zero to logic 1 transission voltage of the
chip ...which is less than 50% rail .... so its going over early ...

I calculate that the threshold must be 1.14V. The range from 0.8V to
2.0V would be TTL limbo, at least for the SN74LS86 device I referred
to in my earlier post.

- Franc Zabkar

 

[Graham]

I calculate that the threshold must be 1.14V. The range from 0.8V to
2.0V would be TTL limbo, at least for the SN74LS86 device I referred
to in my earlier post.

- Franc Zabkar

Well , I have finally found a referance to the cct, in the handbook
for the racal RA1778 hf/rx which uses the cct as a pulse doubling
cct after the main tune shaft encoder , you get a output from the
leading and falling edge of the main pulse .. states the pulse will be
from 0.45 to 1.2 CR ..and gives a wide tolerance .... with cmos
logic .so looks like its a 'bodge' works .. looks quite stable

... the board I have is from the same gang made the same time period ~
1970's

Tnx- G ..