V
~~ VerilogMan ~~
- Jan 1, 1970
- 0
Hello,
I do have a little problem simulating this cir file with pspice (i got it
from
ledit) anyone has an idea ?
I designed a 4bt sequence generator (inverted sequence) and would like to
check it
(I am new with pspice) :|
thanks
*start of file
* Circuit Extracted by Tanner Research's L-Edit Version 8.30 / Extract
Version 8.30 ;
* TDB File: C:\Documents and Settings\George\My
Documents\Goerge\469\xnor.tdb
* Cell: cell0 Version 1.232
* Extract Definition File: nmos2002.ext
* Extract Date and Time: 10/17/2004 - 22:45
* NODE NAME ALIASES
* 1 = Vss (10,-7)
* 2 = OUTPUT (30,14)
* 3 = Vdd (-6,23)
* 5 = B (-24,-2)
* 6 = A (-24,8)
M1 Vss B 8 ? NMOS L=5u W=60u
* M1 DRAIN GATE SOURCE BULK (-16 -4 0 1)
M2 Vss B 7 ? NMOS L=5u W=60u
* M2 DRAIN GATE SOURCE BULK (27 -10 37 1)
M3 OUTPUT 4 7 ? NMOS L=5u W=60u
* M3 DRAIN GATE SOURCE BULK (12 5 34 9)
M4 8 A 4 ? NMOS L=5u W=60u
* M4 DRAIN GATE SOURCE BULK (-16 4 0 9)
M5 Vss A 7 ? NMOS L=5u W=60u
* M5 DRAIN GATE SOURCE BULK (6 -2 22 4)
M6 Vdd Vdd OUTPUT ? NMOS L=10u W=5u
* M6 DRAIN GATE SOURCE BULK (16 13 18 17)
M7 4 Vdd Vdd ? NMOS L=10u W=5u
* M7 DRAIN GATE SOURCE BULK (-14 12 -12 16)
* Total Nodes: 8
* Total Elements: 7
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
..END
I do have a little problem simulating this cir file with pspice (i got it
from
ledit) anyone has an idea ?
I designed a 4bt sequence generator (inverted sequence) and would like to
check it
(I am new with pspice) :|
thanks
*start of file
* Circuit Extracted by Tanner Research's L-Edit Version 8.30 / Extract
Version 8.30 ;
* TDB File: C:\Documents and Settings\George\My
Documents\Goerge\469\xnor.tdb
* Cell: cell0 Version 1.232
* Extract Definition File: nmos2002.ext
* Extract Date and Time: 10/17/2004 - 22:45
* NODE NAME ALIASES
* 1 = Vss (10,-7)
* 2 = OUTPUT (30,14)
* 3 = Vdd (-6,23)
* 5 = B (-24,-2)
* 6 = A (-24,8)
M1 Vss B 8 ? NMOS L=5u W=60u
* M1 DRAIN GATE SOURCE BULK (-16 -4 0 1)
M2 Vss B 7 ? NMOS L=5u W=60u
* M2 DRAIN GATE SOURCE BULK (27 -10 37 1)
M3 OUTPUT 4 7 ? NMOS L=5u W=60u
* M3 DRAIN GATE SOURCE BULK (12 5 34 9)
M4 8 A 4 ? NMOS L=5u W=60u
* M4 DRAIN GATE SOURCE BULK (-16 4 0 9)
M5 Vss A 7 ? NMOS L=5u W=60u
* M5 DRAIN GATE SOURCE BULK (6 -2 22 4)
M6 Vdd Vdd OUTPUT ? NMOS L=10u W=5u
* M6 DRAIN GATE SOURCE BULK (16 13 18 17)
M7 4 Vdd Vdd ? NMOS L=10u W=5u
* M7 DRAIN GATE SOURCE BULK (-14 12 -12 16)
* Total Nodes: 8
* Total Elements: 7
* Total Number of Shorted Elements not written to the SPICE file: 0
* Extract Elapsed Time: 0 seconds
..END