Interpreting Datasheet switching times for MMBTA06

[JH]

Hi, I am having some troubles interpreting the switching time curves
given in the ON semi datasheet for the MMBTA06 NPN transistor. Its
available on the ON website. On pg 3 of the datasheet (fig 4) is a
plot with 4 curves of time vs collector current. They are labeled Tr,
Tf, Ts, and Td. I am assuming that Tr and Tf are rise and fall time,
but what are Ts and Td ? I am guessing T switching and T delay ? I
wish they had put in a timing diagram! I searched on the ON site and
did not turn up any handy application notes explaining the datasheet.

I am trying to calculate the delay time of this part given the way its
biased in the design. Its used to drive a couple FETs as part of a
gate driver. We've measured some unexpectedly long delay time in the
actual circuit from the logic gate and resistors driving the base to
the voltage on the collector and I am trying to understand the
parameters that are affecting that.

Thanks,
Jeff

 

[Joerg]

Hello Jeff,

Hi, I am having some troubles interpreting the switching time curves
given in the ON semi datasheet for the MMBTA06 NPN transistor. Its
available on the ON website. On pg 3 of the datasheet (fig 4) is a
plot with 4 curves of time vs collector current. They are labeled Tr,
Tf, Ts, and Td. I am assuming that Tr and Tf are rise and fall time,
but what are Ts and Td ? I am guessing T switching and T delay ? I
wish they had put in a timing diagram!

Well, that figure is a timing diagram. Td is the delay time and Ts is
the storage time, sometimes also called Tstg. It take time to move
carriers in and out, where "out" is the real challenge in bipolar
transistors. Sometimes that requires the 'sledge hammer' method by
pulling the base negative as much as safely possible. Another more
effective trick is to prevent saturation altogether by 'robbing' base
current just before the transistor reaches that point. This is done via
a Baker Clamp where a Schottky diode robs the base current as the Uce
approaches 200mV.

Regards, Joerg

 

[John Larkin]

Hi, I am having some troubles interpreting the switching time curves
given in the ON semi datasheet for the MMBTA06 NPN transistor. Its
available on the ON website. On pg 3 of the datasheet (fig 4) is a
plot with 4 curves of time vs collector current. They are labeled Tr,
Tf, Ts, and Td. I am assuming that Tr and Tf are rise and fall time,
but what are Ts and Td ? I am guessing T switching and T delay ? I
wish they had put in a timing diagram! I searched on the ON site and
did not turn up any handy application notes explaining the datasheet.

I am trying to calculate the delay time of this part given the way its
biased in the design. Its used to drive a couple FETs as part of a
gate driver. We've measured some unexpectedly long delay time in the
actual circuit from the logic gate and resistors driving the base to
the voltage on the collector and I am trying to understand the
parameters that are affecting that.

Thanks,
Jeff

How much gate swing do you need, and what's the effective gate
capacitance? How fast do you want to go? There are some ICs that would
maybe do the job a lot easier that building your own gate driver.

John

 

[Joerg]

Hello John,

How much gate swing do you need, and what's the effective gate
capacitance? How fast do you want to go? There are some ICs that would
maybe do the job a lot easier that building your own gate driver.

Or use a pnp/npn push-pull pair to swing the gate if there is enough
drive voltage but not enough oomph. That works quite zippy.

Best would be if Jeff could post a schematic.

Regards, Joerg

 

[JH]

Thanks!

I had heard of storage time before but somehow had a mental block on Ts
(duh!). I had it in the back of my mind that storage time was more
related to base current rather than collector current too so maybe
thats the reason for my block... Its been 15yrs since I sat in a
lecture on any of this stuff. This is starting to make more sense now.
The transistor takes about 3us from when the base drive goes low
before we see the collector start to rise. I've calculated the Ic in
the circuit and see that it actually falls off the low end of that
timing curve. The Td is 1us for 15mA Ic (lowest Ic that Ts is defined
and min value on the entire plot is 5mA) and I think we have <2mA.
Given the slope of the Ts line before it falls off the graph I expect
its >>1us for our Ic. I am thinking this part is not the best choice
for this application with such low collector currents.

Jeff

 

[Joerg]

Hello Jeff,

The transistor takes about 3us from when the base drive goes low
before we see the collector start to rise. ...

That's too high. Something else must be going on. Does the FET have a
large gate capacitance?

... I've calculated the Ic in
the circuit and see that it actually falls off the low end of that
timing curve. The Td is 1us for 15mA Ic (lowest Ic that Ts is defined
and min value on the entire plot is 5mA) and I think we have <2mA.
Given the slope of the Ts line before it falls off the graph I expect
its >>1us for our Ic. I am thinking this part is not the best choice
for this application with such low collector currents.

Td should be under 200nsec here so I guess there is something else in
the way. Can you post a schematic? Doesn't have to be the whole
enchilada, just the drive circuit and what it's driving.

Regards, Joerg

 

[JH]

Hi. Unfortunately, I can't post any diagrams.

The MMBTA06 is set up as a common emitter or open collector inverter
and the collector pulls down on a circuit with another MMBTA06 NPN with
a MMBTA56 PNP wired as a current amp in a emitter follower. Those are
arranged to turn on some p channel fets (2 in parallel). The total
Ciss of those is about 7000pF. There are 2 resistors and a zener that
set the gate voltage referenced to the incoming power voltage.
Resistor divider is connected to the common bases of the NPN/PNP. The
zener is to make sure that Vgs of the fets stays <20V. The input
voltage to the fets is variable from 9v to >30v. The NPN/PNP pair are
just there to boost the source/sink current of the divider. The p
channels are used to switch power on or off to another circuit.

I mistyped when I said Td was 1us on the curve for 15mA. I mean't Ts.
The Ts curve falls off the graph for current under 15mA so being at 2mA
I think Ts has to be >1us and could explain the slow turn off.

The p fets turn on pretty fast (<1us) but the turn off is slow, about
5us. About 3us is in the NPN I have been talking about and the other
2us are the NPN/PNP driving the gates and the fets themselves. The
original spec was that both on and off had to be <1us. Some things in
the system changed and the new spec is that the turn off is not too
important anymore so the 5us is "OK" but the turn on now has to be 3us
or more. In working on that, I figured I needed to understand why
things were what they were before I could make changes. The original
designer is not available and I found the design analysis notes that
were left behind are not very good.

Jeff

 

[Joerg]

Hello Jeff,

Hi. Unfortunately, I can't post any diagrams.

If for legal reasons, ok. Else just take a digital camera and then post
it on a.b.s.e. or some free web site. Maybe your employer can give you a
little 'scratch area' on their site (usually they won't).

The MMBTA06 is set up as a common emitter or open collector inverter
and the collector pulls down on a circuit with another MMBTA06 NPN with
a MMBTA56 PNP wired as a current amp in a emitter follower. Those are
arranged to turn on some p channel fets (2 in parallel). The total
Ciss of those is about 7000pF. There are 2 resistors and a zener that
set the gate voltage referenced to the incoming power voltage.
Resistor divider is connected to the common bases of the NPN/PNP. The
zener is to make sure that Vgs of the fets stays <20V. The input
voltage to the fets is variable from 9v to >30v. The NPN/PNP pair are
just there to boost the source/sink current of the divider. The p
channels are used to switch power on or off to another circuit.

That's hard to decipher, even a hand-sketch would make things much
easier. I don't quite get how the current amp can turn on the p-channel
FETs. Anyway, 7000pF is a whole lot of capacitance for that poor MMBTA06
to drive.

I mistyped when I said Td was 1us on the curve for 15mA. I mean't Ts.
The Ts curve falls off the graph for current under 15mA so being at 2mA
I think Ts has to be >1us and could explain the slow turn off.

The p fets turn on pretty fast (<1us) but the turn off is slow, about
5us. About 3us is in the NPN I have been talking about and the other
2us are the NPN/PNP driving the gates and the fets themselves. The
original spec was that both on and off had to be <1us. Some things in
the system changed and the new spec is that the turn off is not too
important anymore so the 5us is "OK" but the turn on now has to be 3us
or more. In working on that, I figured I needed to understand why
things were what they were before I could make changes. The original
designer is not available and I found the design analysis notes that
were left behind are not very good.

That's a situation I deal with a lot, the designer not being there
anymore. Most important is not to rely on device parameters to achieve a
minimum like your new 3usec spec. Best is to have a device or circuit
that is much faster and design in a reliable delay such as RC followed
by a Schmitt. Or two ping-pong delays if on and off times must be
different. At those speeds you could probably even use a little motor
driver half-bridge chip as a driver.

Regards, Joerg

 

[Winfield Hill]

Joerg wrote...

Hello Jeff,

Uh-huh, too lazy? Even proprietary stuff can safely have a snippet
posted, ASCII drawing, etc., especially if it's simple commonplace
circuitry and one is seeking advice about it.

If for legal reasons, ok. Else just take a digital camera and then
post it on a.b.s.e. or some free web site. Maybe your employer can
give you a little 'scratch area' on their site (usually they won't).


That's hard to decipher, even a hand-sketch would make things much
easier. I don't quite get how the current amp can turn on the p-channel
FETs. Anyway, 7000pF is a whole lot of capacitance for that poor
MMBTA06 to drive.

It seems Jeff's driving them with a push-pull emitter-follower pair.

It would appear he's in a scene where the datasheet switching-time
parameters are irrelevant, compare to the other circuit parameters.

Let's help the poor drawing-impaired fellow out. (As usual, Jeff,
use a fixed font like Courier to view the drawing.)

..
.. ------+------+-------+---------,
.. | \_|_ | |
.. Rup /_\ | |
.. | | |/ NPN |
.. +------+-----| |
.. | | |\v |
.. | | | |--S
.. Rdn | +-----|| p-channel
.. | | | |--D MOSFETs
.. | | |/v |
.. |/ NPN '-----| '----
.. ---| |\ PNP
.. |\v |
.. |
.. gnd

We need corrections to my drawing, and resistor + zener values. The
'A06 and A56 transistors are capable of providing 150-200mA of gate
drive output, if they have sufficient base drive. 150mA into 7000pF
would move the gate voltages at i/C = 21V/us, or 0.6us to move 12V.
It appears Jeff's seeing a slower time, so he may benefit from more
base drive. If he reduces the values of Rup and Rdn, he can increase
the current and speedup the MOSFET shutoff, down to the 0.5us limit
of the A06 and A56 capability (they weren't a good choice, due to a
poor high-current beta falloff, but they may be sufficient for Jeff).

At those speeds you could probably even use a little motor
driver half-bridge chip as a driver.

Redesigning to use a decent MOSFET driver IC would be a good idea.

 

[JH]

Well, you got it pretty close....


.. ,------+--------+---------+----VOUT
.. | \_|_ | |
.. 10k /_\ 15v | |
.. | | |/ NPN |
.. +------+------| |___,
.. | | |\v | |
.. | | | |--S _
.. 10k | +-----|| ^ p-channel
.. | | | |--D | MOSFETs
.. | | |/v |___|
.. |/ NPN '------| |
..-4.7k-+-- +---| |\ PNP '----VIN=9--32v
.. | | |\v |
.. 10k C1 | |
.. | | gnd gnd
.. gnd gnd


The circuit seems a little odd since the FETs appear to be in backwards
relative to Vin and Vout. Its intentional for reasons I can't get into
too far. Suffice to say this thing is supposed to act like a rectifier
under some circumstances and a short under others.

The cap C1 is what I have added to increase the FET turn-on delay from
<1us to 3us. I used 2700pf. The turn off is what is pretty slow. The
bottom NPN takes 3us to turn off and the other 2us due to the NPN/PNP
pair with the fets.

About all I can modify right now are the resistors and possibly the
transistors as long as they are the same pkg and pinout. Board can't
be rev'd.

Jeff

 

[Winfield Hill]

JH wrote...

Well, you got it pretty close....

. ,------+--------+---------+----VOUT
. | \_|_ | |
. 10k /_\ 15v | |
. | | |/ NPN |
. +------+------| |___
. | | |\v | |
. | | | |--S _|_
. 10k | +-----|| /_\ p-channel
. | | | |--D | MOSFETs
. | | |/v |___|
. |/ NPN '------| |
. -4.7k-+--+---| |\ PNP '----VIN = 9-32v
. | | |\v |
. 10k C1 | |
. | | gnd gnd
. gnd gnd

The circuit seems a little odd since the FETs appear to be in backwards
relative to Vin and Vout. Its intentional for reasons I can't get into
too far. Suffice to say this thing is supposed to act like a rectifier
under some circumstances and a short under others.

That's a common approach to making an active-assisted power diode.
The MOSFET's substrate diode insures that the output follows Vin
if it's positive, and when you turn on the drive the voltage drop
will be reduced if Vin is high enough and the FETs are big enough.

The cap C1 is what I have added to increase the FET turn-on delay
from <1us to 3us. I used 2700pf.

OK, I see, I had missed that aspect.

The turn off is what is pretty slow. The bottom NPN takes 3us to turn
off and the other 2us due to the NPN/PNP pair with the fets.

About all I can modify right now are the resistors and possibly the
transistors as long as they are the same pkg and pinout. Board can't
be rev'd.

Well, you can reduce the two 10k driving resistors by say 3 to 4x,
right? And if you tack on a reverse diode across the 4.7k you'll
rapidly discharge the added 2700pF. Check the resulting slight
slowing of the input pulse's falltime won't bother something else.

 

[Robert Baer]

Hello Jeff,





Well, that figure is a timing diagram. Td is the delay time and Ts is
the storage time, sometimes also called Tstg. It take time to move
carriers in and out, where "out" is the real challenge in bipolar
transistors. Sometimes that requires the 'sledge hammer' method by
pulling the base negative as much as safely possible. Another more
effective trick is to prevent saturation altogether by 'robbing' base
current just before the transistor reaches that point. This is done via
a Baker Clamp where a Schottky diode robs the base current as the Uce
approaches 200mV.

Regards, Joerg

Well, one can pull current out of the base without the use of a
negative voltage supply.
Alter the base drive and use a resistor in series from driver to NPN
base.
Add a PNP; the base tied to the driver, collector to ground and
emitter to the base of the NPN...one could also try the inverted
configurationby interchanging the emitter and collector.

 

[Joerg]

Hello Robert,

Well, one can pull current out of the base without the use of a
negative voltage supply.
Alter the base drive and use a resistor in series from driver to NPN
base.
Add a PNP; the base tied to the driver, collector to ground and
emitter to the base of the NPN...one could also try the inverted
configurationby interchanging the emitter and collector.

IIUC this wouldn't be able to pull the base closer than 600mV to GND
since the pnp is wired as an emitter follower.

To obtain sufficient charge removal without negative supply I usually
employ a capacitor. Depending on the duty cycle and avaliable swing that
does the job. Of course, the other option would be to use one of those
gold-doped npn transistors. They don't have a lot of beta but they sure
blaze. Nowadays they aren't that expensive anymore.

Regards, Joerg