Tim said:
Yipe. Then, why hasn't someone sued them for falsified information?
lies, damned lies, and shit marketing people make up. read the data
sheet very carefully.
over the last 2 years I've picked a lot of SO-8 substitute FETs. I do
this by calculating Rdson at Tj = 125C. many mfgs dont give you this
figure, they give you the 25C figure and have a scalar curve of
Rdson-vs-Tj. these curves are different, too - so 2 FETs with the same
Rdson at 25C may be quite different at 125C. I've seen scalars ranging
from 1.4 - 1.7. I presume its a function of mfg process, perhaps some of
the semiconductor theorists can explain why. I just know to look carefully.
Well, it kicks an R-S flip-flop, which can only be reset by a pushbutton
wired to supply a couple-microsecond pulse to the reset pin.
jolly good.
Fair enough. Nonetheless, I tested the desat detection circuits and there's
under 10us between a desat pulse and everything inbetween the gate itself
(F/F, '3524, transformer (high side), driver).
OK, next question: how big is the IGBT die? can you dissolve the epoxy
off one of the corpses, and measure it? then we can do a simple
adiabatic heating calc to work out how much time you really have.
volume*density = mass,
mass*specific heat = J/K
pick some suitable dT (eg Tj = 200C is BAD, I use dT = 100C)
now you know how many joules it takes.
divide joules by desat power (bus volts*desat current)
voila, max. desat time.
again. customers even did this often enough to ratchet up the die
Heh heh. It would be nice if I had a 10Gohm resistor on hand, so that 2.7nF
reset pulse generating capacitor can't charge too fast, but alas...
Sooo, it's more like an SCR? Once-per-IGBT-SCR? So what happens if I push
1mA CCSource into the collector, will voltage rise to ~600V then kill to 0
or 2V? Will it stabilize like a zener? How about 10mA? 100?
hopefully Win or someone will step in and answer this - I cant. I have
read some papers on this, but all I can remember is DONT DO IT.
the only igbts I have lying around are 600A 1200V parts, and I'm not
willing to sacrifice them....
What if I make L go to shit, and make a shorting-commutating bridge? Izzat
much safer for this stuff?
its just different. then you have the converse problem - turn all igbts
off and kaboom.
philosophically, it is usually a bad idea to throw out an entire design
when one runs into problems - the learning (lifetime) curve resets, and
now you get to discover all the problems with the new design. far better
to measure the amount of funny. As long as the basic topology isnt too
unsuited to the task, the problems can usually be fixed.
that being said, sometimes the answer is to throw it out and start
again, but IME thats not usually the case.
Although I have worked with a number of people who routinely do this
(abandon entire designs) and their hardware is *always* in a state of
"dodgy prototype". Never hire such people. If you do, fire them. the
technical term is "idiot"
Well...yeah...fine... 4.5" each way (end to end), plus film caps in the
middle, plus about 1/2" max. seperation between the strips.
what you want to do is get, say, 1mm lexan, and place your strips on
either side of that, with the lexan somewhat wider than the strips
(clearance, 3-6mm ought to do). just like a 2-sided PCB.
I'll guess its 1mm thick, and 1" wide strip.
according to Terman, Radio Engineers Handbook, p.52:
l = 4.5"
b = 1"
c = (1/25.4)"
D = 0.5" + 1"/2 + 1"/2 = 1.5"
L = 0.1016*l*[ln(D/(b+c)) + 1.5 - D/l + 0.2235*(b+c)/l) uH
{ 2.303*log() = ln() }
L = 0.1016*4.5*[0.36685 + 1.5 - 0.333 + 0.0516] uH
L = 724nH
its pretty clear that strip thickness c does bugger all.
for 0.5" wide strip, b = 0.5" and D = 1" so L = 879nH
thats a lot.
the inductance of the film caps is also not negligible. it would be
reasonable to slice the bus inductance into n identical sections, each
feeding a cap then the next section. you could then quickly hack up a
spice simulation, and measure the effective inductance seen looking into
the end of the strip.
its fairly easy to measure the cap ESL, hell the mfg may even tell you
the SRF. betcha its 10nH or more though, but probably < 30nH.
anytime in the next 8-12 seconds would be fine
the next important thing is the half-bridge interconnects. the upper
IGBT collector could (should) bolt directly to the +Vdc strip, but then
you need to connect its emitter (luckily, this is a long skinny leg, so
as to maximise its inductance) to the collector of the lower IGBT, whose
emitter ought to connect directly to the -Vdc strip.
crazy thought:
bend upper E leg over top of case, solder wide strip to it (the folding
will help cancel out the inductance). then sit lower IGBT on top of
this, solder it up, and do a similar trick for its E, running the wide
strip down to the -Vdc bus. best not to think about the heatsinking
(until you realise that making the strip very thick does bugger all to
L, in which case it morphs into a heat spreader/sink).
you can now see why I use multilayer structures (2mm Cu plates & lexan
for big stuff, 10Oz pcb for little stuff, 1-4Oz pcb for toys).
with single powerex U-series IGBTs arranged as a half-bridge, there is
another great trick. after you kill one, gut it. then you will see how
the module internal bus-bars run - up one side of the module. Re-do your
half-bridge layout such that the internal bus-bars of each IGBT are as
close together as possible - IOW spin one IGBT 180 degrees. this
minimises the total inductance. If not, you just placed the two internal
bus bars 160mm apart (c.f. 5mm), thereby maximising the total
inductance, and ensuring that in the event of a desat (and perhaps even
during normal operation) kaboom
What significance is a TL at these edge rates? I'm not doing anything
nanosecondey here.
bloody low L. for a parallel plate transmission line, width b,
separation a, L = Uo*b/a, Uo = 1.2566*uH/m (R,W,vD p.250 table 5.11b)
25.4mm wide, 1mm spacing, L = 50nH/m.
4.5" of this TL is 1.26nH, which pisses all over your 0.5" spaced
strips, by almost 3 orders of magnitude
remember, a transmission line is a lumped circuit element for l <
lambda/20 (ish), as in your case, and as you can see, its a damned good one!
If the goal is to add distributed capacitance to slow e.g. flyback pulses,
wouldn't a small (say 0.047uF) cap at each IGBT be more effective?
yes. but the cap L must be low. if you use a 1" long film cap, it'll
have quite high L. special "IGBT snubber" caps exist (often designed to
bolt directly to the IGBT terminals) with inductances on the order of 1-2nH.
If you use a pcb, then you can plop down HV smt caps (dont hand-solder
them lest they EXPLODE) which are dirt cheap, and have about 1nH ESL
(it'll be at least a 1206 package, perhaps bigger).
beware smt film caps though - some (WIMA IIRC) are actually leaded caps,
legs bent alongside body, and metal plates welded on. so the inductance
is really no better than the leaded cap itself.
How
about 10-20 spaced evenly along the strip?
see above wrt inductance of each piece of strip.
I've got a paper somewhere (buried under huge pile of shit no doubt)
where it is "proven" that valves always beat silicon at high enough
power levels, cos they can get a lot hotter. roll on SiC.
Cheers
Terry